component
74HC30S
Public Made by Adomby adom
GR Gates, SOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
orderable attributes: rebuild .lbr with adom-lbr 2.18.0 so MPN, MANUFACTURER and the distributor part numbers reach <technology> (LCSC_PN C19818870). The published library carried no attributes at all, so a BOM had nothing to buy from. Distributor PNs matched on exact MPN AND corroborating manufacturer.
2 files changed
+32−12
74hc30s.lbr+20−2@@ -68,6 +68,18 @@ <smd name="12" x="2.4750" y="1.2700" dx="1.9500" dy="0.6000" layer="1"/> <smd name="13" x="2.4750" y="2.5400" dx="1.9500" dy="0.6000" layer="1"/> <smd name="14" x="2.4750" y="3.8100" dx="1.9500" dy="0.6000" layer="1"/>+ <polygon width="0.1200" layer="21">+ <vertex x="-2.6000" y="4.3700"/>+ <vertex x="-2.8400" y="4.7000"/>+ <vertex x="-2.3600" y="4.7000"/>+ </polygon>+ <polygon width="0.1000" layer="51">+ <vertex x="-0.9750" y="4.3250"/>+ <vertex x="1.9500" y="4.3250"/>+ <vertex x="1.9500" y="-4.3250"/>+ <vertex x="-1.9500" y="-4.3250"/>+ <vertex x="-1.9500" y="3.3500"/>+ </polygon> <wire x1="-2.0600" y1="4.4350" x2="2.0600" y2="4.4350" width="0.1200" layer="21"/> <wire x1="-2.0600" y1="4.3700" x2="-2.0600" y2="4.4350" width="0.1200" layer="21"/> <wire x1="-2.0600" y1="-4.4350" x2="-2.0600" y2="-4.3700" width="0.1200" layer="21"/>@@ -76,7 +88,7 @@ <wire x1="2.0600" y1="-4.4350" x2="-2.0600" y2="-4.4350" width="0.1200" layer="21"/> <text x="0" y="5.385" size="1.27" layer="25" align="bottom-center">>NAME</text> <text x="0" y="-5.385" size="1.27" layer="27" align="top-center">>VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-2.6000" y="4.3700"/><vertex x="-2.8400" y="4.7000"/><vertex x="-2.3600" y="4.7000"/></polygon></package>+</package> </packages> <symbols> <symbol name="74HC30S">@@ -126,7 +138,13 @@ <connect gate="G$1" pin="NC@3" pad="9"/> <connect gate="G$1" pin="Y" pad="8"/> </connects>- <technologies><technology name=""/></technologies>+ <technologies>+ <technology name="">+ <attribute name="MPN" value="74HC30S" constant="no"/>+ <attribute name="MANUFACTURER" value="GR" constant="no"/>+ <attribute name="LCSC_PN" value="C19818870" constant="no"/>+ </technology>+ </technologies> </device> </devices> </deviceset>
page.json+12−10@@ -26,43 +26,45 @@ "model_3d_step": "74hc30s.step", "lbr": "74hc30s.lbr" },- "distributor_links": {},+ "distributor_links": {+ "lcsc": "C19818870"+ }, "pins": [ { "number": "1", "name": "A", "type": "input",- "description": "NAND gate input A. CMOS logic input; VIH ≥ 4.2 V and VIL ≤ 1.8 V at VCC = 6 V. Input current ≤ 1 µA."+ "description": "NAND gate input A. CMOS logic input; VIH \u2265 4.2 V and VIL \u2264 1.8 V at VCC = 6 V. Input current \u2264 1 \u00b5A." }, { "number": "2", "name": "B", "type": "input",- "description": "NAND gate input B. CMOS logic input; VIH ≥ 4.2 V and VIL ≤ 1.8 V at VCC = 6 V. Input current ≤ 1 µA."+ "description": "NAND gate input B. CMOS logic input; VIH \u2265 4.2 V and VIL \u2264 1.8 V at VCC = 6 V. Input current \u2264 1 \u00b5A." }, { "number": "3", "name": "C", "type": "input",- "description": "NAND gate input C. CMOS logic input; VIH ≥ 4.2 V and VIL ≤ 1.8 V at VCC = 6 V. Input current ≤ 1 µA."+ "description": "NAND gate input C. CMOS logic input; VIH \u2265 4.2 V and VIL \u2264 1.8 V at VCC = 6 V. Input current \u2264 1 \u00b5A." }, { "number": "4", "name": "D", "type": "input",- "description": "NAND gate input D. CMOS logic input; VIH ≥ 4.2 V and VIL ≤ 1.8 V at VCC = 6 V. Input current ≤ 1 µA."+ "description": "NAND gate input D. CMOS logic input; VIH \u2265 4.2 V and VIL \u2264 1.8 V at VCC = 6 V. Input current \u2264 1 \u00b5A." }, { "number": "5", "name": "E", "type": "input",- "description": "NAND gate input E. CMOS logic input; VIH ≥ 4.2 V and VIL ≤ 1.8 V at VCC = 6 V. Input current ≤ 1 µA."+ "description": "NAND gate input E. CMOS logic input; VIH \u2265 4.2 V and VIL \u2264 1.8 V at VCC = 6 V. Input current \u2264 1 \u00b5A." }, { "number": "6", "name": "F", "type": "input",- "description": "NAND gate input F. CMOS logic input; VIH ≥ 4.2 V and VIL ≤ 1.8 V at VCC = 6 V. Input current ≤ 1 µA."+ "description": "NAND gate input F. CMOS logic input; VIH \u2265 4.2 V and VIL \u2264 1.8 V at VCC = 6 V. Input current \u2264 1 \u00b5A." }, { "number": "7",@@ -74,7 +76,7 @@ "number": "8", "name": "Y", "type": "output",- "description": "8-input NAND gate output Y = NOT(A·B·C·D·E·F·G·H). Buffered push-pull CMOS output; sources/sinks up to 4.0 mA at VCC=4.5 V and 5.2 mA at VCC=6.0 V. Absolute-max IOUT ±25 mA."+ "description": "8-input NAND gate output Y = NOT(A\u00b7B\u00b7C\u00b7D\u00b7E\u00b7F\u00b7G\u00b7H). Buffered push-pull CMOS output; sources/sinks up to 4.0 mA at VCC=4.5 V and 5.2 mA at VCC=6.0 V. Absolute-max IOUT \u00b125 mA." }, { "number": "9",@@ -92,13 +94,13 @@ "number": "11", "name": "G", "type": "input",- "description": "NAND gate input G. CMOS logic input; VIH ≥ 4.2 V and VIL ≤ 1.8 V at VCC = 6 V. Input current ≤ 1 µA."+ "description": "NAND gate input G. CMOS logic input; VIH \u2265 4.2 V and VIL \u2264 1.8 V at VCC = 6 V. Input current \u2264 1 \u00b5A." }, { "number": "12", "name": "H", "type": "input",- "description": "NAND gate input H. CMOS logic input; VIH ≥ 4.2 V and VIL ≤ 1.8 V at VCC = 6 V. Input current ≤ 1 µA."+ "description": "NAND gate input H. CMOS logic input; VIH \u2265 4.2 V and VIL \u2264 1.8 V at VCC = 6 V. Input current \u2264 1 \u00b5A." }, { "number": "13",