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74HC30PW-Q100J

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Nexperia Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74HC30PW-Q100J

Nexperia · Logic Gates · TSSOP-14

74HC30PW-Q100J from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A input Data input A of the 8-input NAND gate; inputs include clamp diodes so current-limiting resistors can interface inputs to voltages above VCC.
2 B input Data input B of the 8-input NAND gate; inputs include clamp diodes so current-limiting resistors can interface inputs to voltages above VCC.
3 C input Data input C of the 8-input NAND gate; inputs include clamp diodes so current-limiting resistors can interface inputs to voltages above VCC.
4 D input Data input D of the 8-input NAND gate; inputs include clamp diodes so current-limiting resistors can interface inputs to voltages above VCC.
5 E input Data input E of the 8-input NAND gate; inputs include clamp diodes so current-limiting resistors can interface inputs to voltages above VCC.
6 F input Data input F of the 8-input NAND gate; inputs include clamp diodes so current-limiting resistors can interface inputs to voltages above VCC.
7 GND power_in Ground (0 V) reference for all voltages in the device.
8 Y output NAND data output; Y is HIGH if any input is LOW and LOW only when all eight inputs are HIGH (per the function table).
9 n.c. unconnected Not connected internally.
10 n.c. unconnected Not connected internally.
11 G input Data input G of the 8-input NAND gate; inputs include clamp diodes so current-limiting resistors can interface inputs to voltages above VCC.
12 H input Data input H of the 8-input NAND gate; inputs include clamp diodes so current-limiting resistors can interface inputs to voltages above VCC.
13 n.c. unconnected Not connected internally.
14 VCC power_in Supply voltage; 2.0 V to 6.0 V for 74HC30-Q100 and 4.5 V to 5.5 V for 74HCT30-Q100 (recommended operating conditions), absolute maximum 7 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 7 V 4
input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 4
output current IO -25 25 mA -0.5 V < VO < VCC + 0.5 V 4
supply current ICC 50 mA 4
ground current IGND -50 mA 4
storage temperature Tstg -65 150 °C 4
total power dissipation Ptot 500 mW SOT402-1 (TSSOP14): derates linearly 7.3 mW/K above 81 °C 4
supply voltage VCC 2 5 6 V 4
input voltage VI 0 V max printed as VCC 4
output voltage VO 0 V max printed as VCC 4
ambient temperature Tamb -40 125 °C 4
input transition rise and fall rate Δt/ΔV 625 ns/V VCC = 2.0 V 4
input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 4
input transition rise and fall rate Δt/ΔV 83 ns/V VCC = 6.0 V 4
HIGH-level input voltage VIH 1.5 1.2 V VCC = 2.0 V 5
HIGH-level input voltage VIH 3.15 2.4 V VCC = 4.5 V 5
HIGH-level input voltage VIH 4.2 3.2 V VCC = 6.0 V 5
LOW-level input voltage VIL 0.8 0.5 V VCC = 2.0 V 5
LOW-level input voltage VIL 2.1 1.35 V VCC = 4.5 V 5
LOW-level input voltage VIL 2.8 1.8 V VCC = 6.0 V 5
HIGH-level output voltage VOH 1.9 2 V VI = VIH or VIL; IO = -20 μA; VCC = 2.0 V 5
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V 5
HIGH-level output voltage VOH 5.9 6 V VI = VIH or VIL; IO = -20 μA; VCC = 6.0 V 5
HIGH-level output voltage VOH 3.7 4.32 V VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V 5
HIGH-level output voltage VOH 5.2 5.81 V VI = VIH or VIL; IO = -5.2 mA; VCC = 6.0 V 5
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V 5
LOW-level output voltage VOL 0.15 0.4 V VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V 5
LOW-level output voltage VOL 0.16 0.4 V VI = VIH or VIL; IO = 5.2 mA; VCC = 6.0 V 5
input leakage current II -1 1 μA VI = VCC or GND; VCC = 6.0 V 5
supply current ICC 40 μA VI = VCC or GND; IO = 0 A; VCC = 6.0 V 5
propagation delay tpd 41 195 ns CL = 50 pF; VCC = 2.0 V; see Fig. 5 6
propagation delay tpd 15 39 ns CL = 50 pF; VCC = 4.5 V; see Fig. 5 6
propagation delay tpd 12 33 ns CL = 50 pF; VCC = 6.0 V; see Fig. 5 6
transition time tt 19 110 ns CL = 50 pF; VCC = 2.0 V; see Fig. 5 6
transition time tt 7 22 ns CL = 50 pF; VCC = 4.5 V; see Fig. 5 6
transition time tt 6 19 ns CL = 50 pF; VCC = 6.0 V; see Fig. 5 6

CAD (KiCad official)

  • Symbol: 74HC30PW-Q100J
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: 74hc30pw-q100j-etched.step / 74hc30pw-q100j-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc30pw-q100j.step / 74hc30pw-q100j.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (13 pp, sha256 73ce360c3809095f, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF