# 74HC30D

**Nexperia** · Logic Gates · SOIC-14

74HC30D from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Data input of the 8-input NAND gate; inputs include clamp diodes so current-limiting resistors can interface voltages above VCC, with input clamping current limited to ±20 mA. |
| 2 | B | input | Data input of the 8-input NAND gate; inputs include clamp diodes so current-limiting resistors can interface voltages above VCC, with input clamping current limited to ±20 mA. |
| 3 | C | input | Data input of the 8-input NAND gate; inputs include clamp diodes so current-limiting resistors can interface voltages above VCC, with input clamping current limited to ±20 mA. |
| 4 | D | input | Data input of the 8-input NAND gate; inputs include clamp diodes so current-limiting resistors can interface voltages above VCC, with input clamping current limited to ±20 mA. |
| 5 | E | input | Data input of the 8-input NAND gate; inputs include clamp diodes so current-limiting resistors can interface voltages above VCC, with input clamping current limited to ±20 mA. |
| 6 | F | input | Data input of the 8-input NAND gate; inputs include clamp diodes so current-limiting resistors can interface voltages above VCC, with input clamping current limited to ±20 mA. |
| 7 | GND | power_in | Ground reference, 0 V; all voltages are referenced to GND. |
| 8 | Y | output | NAND data output, HIGH unless all eight inputs are HIGH; output current limited to ±25 mA for -0.5 V < VO < VCC + 0.5 V. |
| 9 | n.c. | unconnected | Not connected. |
| 10 | n.c. | unconnected | Not connected. |
| 11 | G | input | Data input of the 8-input NAND gate; inputs include clamp diodes so current-limiting resistors can interface voltages above VCC, with input clamping current limited to ±20 mA. |
| 12 | H | input | Data input of the 8-input NAND gate; inputs include clamp diodes so current-limiting resistors can interface voltages above VCC, with input clamping current limited to ±20 mA. |
| 13 | n.c. | unconnected | Not connected. |
| 14 | VCC | power_in | Supply voltage; 74HC30 operates from 2.0 V to 6.0 V and 74HCT30 from 4.5 V to 5.5 V, with VCC absolute maximum of -0.5 V to +7 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |

## CAD (KiCad official)

- Symbol: `74HC30D`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files: `74hc30d-etched.step` / `74hc30d-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74hc30d.step` / `74hc30d.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Nexperia datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8555344465392336896) (13 pp, sha256 `461f481b50017bf4`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/74hc30d-datasheet.pdf)