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74HC27S

Public Made by Adom

by adom

GR Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74HC27S

GR · Logic Gates · SOP-14

74HC27S from GR, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A1 input Input A of NOR gate 1; the input voltage must stay between -0.3 V and VCC+0.3 V (absolute maximum ratings).
2 B1 input Input B of NOR gate 1; the input voltage must stay between -0.3 V and VCC+0.3 V (absolute maximum ratings).
3 A2 input Input A of NOR gate 2; the input voltage must stay between -0.3 V and VCC+0.3 V (absolute maximum ratings).
4 B2 input Input B of NOR gate 2; the input voltage must stay between -0.3 V and VCC+0.3 V (absolute maximum ratings).
5 C2 input Input C of NOR gate 2; the input voltage must stay between -0.3 V and VCC+0.3 V (absolute maximum ratings).
6 Y2 output Buffered push-pull output of NOR gate 2; the absolute maximum output current per pin is 25 mA.
7 GND power_in Ground reference for the device.
8 Y3 output Buffered push-pull output of NOR gate 3; the absolute maximum output current per pin is 25 mA.
9 A3 input Input A of NOR gate 3; the input voltage must stay between -0.3 V and VCC+0.3 V (absolute maximum ratings).
10 B3 input Input B of NOR gate 3; the input voltage must stay between -0.3 V and VCC+0.3 V (absolute maximum ratings).
11 C3 input Input C of NOR gate 3; the input voltage must stay between -0.3 V and VCC+0.3 V (absolute maximum ratings).
12 Y1 output Buffered push-pull output of NOR gate 1; the absolute maximum output current per pin is 25 mA.
13 C1 input Input C of NOR gate 1; the input voltage must stay between -0.3 V and VCC+0.3 V (absolute maximum ratings).
14 VCC power_in Positive supply; the datasheet gives an operating range of 2.0 V to 6.0 V and an absolute maximum of 6.5 V.

Key specifications

Parameter Value
Manufacturer GR
Package SOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Low-level input voltage VIL 0.5 V VCC=2.0V 2
Low-level input voltage VIL 1.35 V VCC=4.5V 2
Low-level input voltage VIL 1.8 V VCC=6.0V 2
High-level input voltage VIH 1.5 V VCC=2.0V 2
High-level input voltage VIH 3.15 V VCC=4.5V 2
High-level input voltage VIH 4.2 V VCC=6.0V 2
High-level output voltage VOH 1.9 V VI=VIH or VIL, /IOUT/≤20μA, VCC=2.0V 2
High-level output voltage VOH 4.4 V VI=VIH or VIL, /IOUT/≤20μA, VCC=4.5V 2
High-level output voltage VOH 5.9 V VI=VIH or VIL, /IOUT/≤20μA, VCC=6.0V 2
High-level output voltage VOH 3.7 4.4 V VI=VIH, /IOUT/≤4.0mA, VCC=4.5V 2
High-level output voltage VOH 5.2 5.8 V VI=VIH, /IOUT/≤5.2mA, VCC=6.0V 2
Low-level output voltage VOL 0.1 V VI=VIH or VIL, /IOUT/≤20μA, VCC=2.0V 2
Low-level output voltage VOL 0.06 0.4 V VI=VIH, /IOUT/≤4.0mA, VCC=4.5V 2
Low-level output voltage VOL 0.07 0.5 V VI=VIH, /IOUT/≤5.2mA, VCC=6.0V 2
Input current IIN 1 uA VI=VCC or GND, VCC=6.0V 2
Operating current ICC 5.5 uA VI=VCC or GND, IOUT=0μA, VCC=6.0V 2
Maximum propagation delay time A, B, C to Y (high-to-low) tPHL 20 ns Ta=25℃, VCC=5.0V, tr=tf≤20ns, CL=15pF 3
Maximum propagation delay time A, B, C to Y (low-to-high) tPLH 25 ns Ta=25℃, VCC=5.0V, tr=tf≤20ns, CL=15pF 3
Supply voltage VCC VCC 2 5 6 V 2
Input/output voltage VIN, VOUT 0 V upper limit printed as VCC 2
Input rise/fall time Tr, tf Tr, tf 0 1000 ns VCC=2.0V 2
Input rise/fall time Tr, tf Tr, tf 0 500 ns VCC=4.5V 2
Input rise/fall time Tr, tf Tr, tf 0 400 ns VCC=6.0V 2
Operating temperature TA TA 0 60 ℃ 2
Supply voltage VCC VCC 6.5 V 1
Input/output voltage VIN, VOUT -0.3 V upper limit printed as Vcc+0.3 V 1
Output current per pin IOUT 25 mA 1
VCC or GND current ICC 50 mA 1
Power dissipation PD 500 mW 1
Operating temperature TA 0 70 ℃ 1
Storage temperature TS -65 150 ℃ 1
Lead soldering temperature TW 260 ℃ 10 s 1

CAD (KiCad official)

  • Symbol: 74HC27S
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: 74hc27s-etched.step / 74hc27s-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc27s.step / 74hc27s.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: GR datasheet (5 pp, sha256 9428b3921deb0a3e, retrieved 2026-10-20, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF