component
74HC27D
Public Made by Adomby adom
Nexperia Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74HC27D
Nexperia · Logic Gates · SOIC-14
74HC27D from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input 1A of NOR gate 1; output 1Y is HIGH only when 1A, 1B and 1C are all LOW, and input voltage must stay within 0 V to VCC (Tables 3 and 5). |
| 2 | 1B | input | Data input 1B of NOR gate 1; output 1Y is HIGH only when 1A, 1B and 1C are all LOW, and input voltage must stay within 0 V to VCC (Tables 3 and 5). |
| 3 | 2A | input | Data input 2A of NOR gate 2; output 2Y is HIGH only when 2A, 2B and 2C are all LOW, and input voltage must stay within 0 V to VCC (Tables 3 and 5). |
| 4 | 2B | input | Data input 2B of NOR gate 2; output 2Y is HIGH only when 2A, 2B and 2C are all LOW, and input voltage must stay within 0 V to VCC (Tables 3 and 5). |
| 5 | 2C | input | Data input 2C of NOR gate 2; output 2Y is HIGH only when 2A, 2B and 2C are all LOW, and input voltage must stay within 0 V to VCC (Tables 3 and 5). |
| 6 | 2Y | output | Data output 2Y of NOR gate 2; output current is limited to ±25 mA (Table 4). |
| 7 | GND | power_in | Ground (0 V) reference for all voltages on the device (Table 2 and Table 4). |
| 8 | 3Y | output | Data output 3Y of NOR gate 3; output current is limited to ±25 mA (Table 4). |
| 9 | 3A | input | Data input 3A of NOR gate 3; output 3Y is HIGH only when 3A, 3B and 3C are all LOW, and input voltage must stay within 0 V to VCC (Tables 3 and 5). |
| 10 | 3B | input | Data input 3B of NOR gate 3; output 3Y is HIGH only when 3A, 3B and 3C are all LOW, and input voltage must stay within 0 V to VCC (Tables 3 and 5). |
| 11 | 3C | input | Data input 3C of NOR gate 3; output 3Y is HIGH only when 3A, 3B and 3C are all LOW, and input voltage must stay within 0 V to VCC (Tables 3 and 5). |
| 12 | 1Y | output | Data output 1Y of NOR gate 1; output current is limited to ±25 mA (Table 4). |
| 13 | 1C | input | Data input 1C of NOR gate 1; output 1Y is HIGH only when 1A, 1B and 1C are all LOW, and input voltage must stay within 0 V to VCC (Tables 3 and 5). |
| 14 | VCC | power_in | Supply voltage: 2.0 V to 6.0 V for 74HC27 and 4.5 V to 5.5 V for 74HCT27 (recommended), with an absolute maximum of +7 V (Tables 4 and 5). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 3 | ||
| Input clamping current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 3 | |
| Output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 3 | |
| Output current | IO | -25 | 25 | mA | -0.5 V < VO < VCC + 0.5 V | 3 | |
| Supply current | ICC | 50 | mA | 3 | |||
| Ground current | IGND | -50 | mA | 3 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| Total power dissipation | Ptot | 500 | mW | 3 | |||
| Supply voltage | VCC | 2 | 5 | 6 | V | 74HC27 | 3 |
| Input voltage | VI | 0 | V | 74HC27; maximum printed as VCC | 3 | ||
| Output voltage | VO | 0 | V | 74HC27; maximum printed as VCC | 3 | ||
| Ambient temperature | Tamb | -40 | 25 | 125 | °C | 74HC27 | 3 |
| Input transition rise and fall rate | Δt/ΔV | 625 | ns/V | VCC = 2.0 V | 3 | ||
| Input transition rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC = 4.5 V | 3 | |
| Input transition rise and fall rate | Δt/ΔV | 83 | ns/V | VCC = 6.0 V | 3 | ||
| HIGH-level input voltage | VIH | 1.5 | 1.2 | V | VCC = 2.0 V; -40 °C to +125 °C (typ at 25 °C) | 4 | |
| HIGH-level input voltage | VIH | 3.15 | 2.4 | V | VCC = 4.5 V; -40 °C to +125 °C (typ at 25 °C) | 4 | |
| HIGH-level input voltage | VIH | 4.2 | 3.2 | V | VCC = 6.0 V; -40 °C to +125 °C (typ at 25 °C) | 4 | |
| LOW-level input voltage | VIL | 0.8 | 0.5 | V | VCC = 2.0 V; -40 °C to +125 °C (typ at 25 °C) | 4 | |
| LOW-level input voltage | VIL | 2.1 | 1.35 | V | VCC = 4.5 V; -40 °C to +125 °C (typ at 25 °C) | 4 | |
| LOW-level input voltage | VIL | 2.8 | 1.8 | V | VCC = 6.0 V; -40 °C to +125 °C (typ at 25 °C) | 4 | |
| HIGH-level output voltage | VOH | 1.9 | 2 | V | VI = VIH or VIL; IO = -20 μA; VCC = 2.0 V; -40 °C to +125 °C (typ at 25 °C) | 4 | |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V; -40 °C to +125 °C (typ at 25 °C) | 4 | |
| HIGH-level output voltage | VOH | 5.9 | 6 | V | VI = VIH or VIL; IO = -20 μA; VCC = 6.0 V; -40 °C to +125 °C (typ at 25 °C) | 4 | |
| HIGH-level output voltage | VOH | 3.7 | 4.32 | V | VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V; -40 °C to +125 °C (typ at 25 °C) | 4 | |
| HIGH-level output voltage | VOH | 5.2 | 5.81 | V | VI = VIH or VIL; IO = -5.2 mA; VCC = 6.0 V; -40 °C to +125 °C (typ at 25 °C) | 4 | |
| LOW-level output voltage | VOL | 0 | 0.1 | V | VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V; -40 °C to +125 °C (typ at 25 °C) | 4 | |
| LOW-level output voltage | VOL | 0.15 | 0.4 | V | VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V; -40 °C to +125 °C (typ at 25 °C) | 4 | |
| LOW-level output voltage | VOL | 0.16 | 0.4 | V | VI = VIH or VIL; IO = 5.2 mA; VCC = 6.0 V; -40 °C to +125 °C (typ at 25 °C) | 4 | |
| Input leakage current | II | -1 | 1 | μA | VI = VCC or GND; VCC = 6.0 V; -40 °C to +125 °C | 4 | |
| Supply current | ICC | 40 | μA | VI = VCC or GND; IO = 0 A; VCC = 6.0 V; -40 °C to +125 °C | 4 | ||
| Propagation delay nA, nB, nC to nY | tpd | 28 | 135 | ns | VCC = 2.0 V; see Fig. 4; -40 °C to +125 °C (typ at 25 °C) | 5 | |
| Propagation delay nA, nB, nC to nY | tpd | 10 | 27 | ns | VCC = 4.5 V; see Fig. 4; -40 °C to +125 °C (typ at 25 °C) | 5 | |
| Propagation delay nA, nB, nC to nY | tpd | 8 | 23 | ns | VCC = 6.0 V; see Fig. 4; -40 °C to +125 °C (typ at 25 °C) | 5 | |
| Transition time | tt | 19 | 110 | ns | VCC = 2.0 V; see Fig. 4; -40 °C to +125 °C (typ at 25 °C) | 5 | |
| Transition time | tt | 7 | 22 | ns | VCC = 4.5 V; see Fig. 4; -40 °C to +125 °C (typ at 25 °C) | 5 | |
| Transition time | tt | 6 | 19 | ns | VCC = 6.0 V; see Fig. 4; -40 °C to +125 °C (typ at 25 °C) | 5 |
CAD (KiCad official)
- Symbol:
74HC27D - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
74hc27d-etched.step/74hc27d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc27d.step/74hc27d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (12 pp, sha256
6996b48ab9e68d6b, retrieved 2026-10-17, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).