component
74HC273M
Public Made by Adomby adom
HGSEMI Flip Flops, SOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 5d ago |
| viewers | 5d ago |
| 74hc273m-etched.glb | 5d ago |
| 74hc273m-etched.step | 5d ago |
| 74hc273m-hero.glb | 5d ago |
| 74hc273m-hero.overlay.json | 5d ago |
| 74hc273m.glb | 5d ago |
| 74hc273m.kicad_mod | 5d ago |
| 74hc273m.kicad_sym | 5d ago |
| 74hc273m.lbr | 5d ago |
| 74hc273m.step | 5d ago |
| package.json | 5d ago |
| page.json | 5d ago |
| README.md | 5d ago |
74HC273M
HGSEMI · Flip Flops · SOP-20
74HC273M from HGSEMI, in a SOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MR | input | Master reset input, active low; when low, all Qn outputs are forced low regardless of CP and Dn. |
| 2 | Q0 | output | Flip-flop 0 output, which takes the D0 value on the low-to-high CP transition and is held low while MR is low. |
| 3 | D0 | input | Data input for flip-flop 0, which must meet the Dn-to-CP setup and hold times around the rising CP edge. |
| 4 | D1 | input | Data input for flip-flop 1, which must meet the Dn-to-CP setup and hold times around the rising CP edge. |
| 5 | Q1 | output | Flip-flop 1 output, which takes the D1 value on the low-to-high CP transition and is held low while MR is low. |
| 6 | Q2 | output | Flip-flop 2 output, which takes the D2 value on the low-to-high CP transition and is held low while MR is low. |
| 7 | D2 | input | Data input for flip-flop 2, which must meet the Dn-to-CP setup and hold times around the rising CP edge. |
| 8 | D3 | input | Data input for flip-flop 3, which must meet the Dn-to-CP setup and hold times around the rising CP edge. |
| 9 | Q3 | output | Flip-flop 3 output, which takes the D3 value on the low-to-high CP transition and is held low while MR is low. |
| 10 | GND | power_in | Ground reference, 0 V. |
| 11 | CP | input | Clock input; all eight flip-flops capture their Dn data on the low-to-high transition. |
| 12 | Q4 | output | Flip-flop 4 output, which takes the D4 value on the low-to-high CP transition and is held low while MR is low. |
| 13 | D4 | input | Data input for flip-flop 4, which must meet the Dn-to-CP setup and hold times around the rising CP edge. |
| 14 | D5 | input | Data input for flip-flop 5, which must meet the Dn-to-CP setup and hold times around the rising CP edge. |
| 15 | Q5 | output | Flip-flop 5 output, which takes the D5 value on the low-to-high CP transition and is held low while MR is low. |
| 16 | Q6 | output | Flip-flop 6 output, which takes the D6 value on the low-to-high CP transition and is held low while MR is low. |
| 17 | D6 | input | Data input for flip-flop 6, which must meet the Dn-to-CP setup and hold times around the rising CP edge. |
| 18 | D7 | input | Data input for flip-flop 7, which must meet the Dn-to-CP setup and hold times around the rising CP edge. |
| 19 | Q7 | output | Flip-flop 7 output, which takes the D7 value on the low-to-high CP transition and is held low while MR is low. |
| 20 | VCC | power_in | Positive supply; recommended range 2.0 V to 6.0 V, absolute maximum 7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HGSEMI |
| Package | SOP-20 |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 5 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI<-0.5V or VI>VCC+0.5V | 5 | |
| Output clamp current | IOK | -20 | 20 | mA | VO<-0.5V or VO>VCC+0.5V | 5 | |
| Output current | IO | -25 | 25 | mA | -0.5V<VO<VCC+0.5V | 5 | |
| Supply current | ICC | 50 | mA | 5 | |||
| Ground current | IGND | -50 | mA | 5 | |||
| Storage temperature | Tstg | -65 | 150 | ℃ | 5 | ||
| Total power dissipation | Ptot | 500 | mW | 5 | |||
| Soldering temperature | TL | 250 | ℃ | 10 s, SOP | 5 | ||
| Supply voltage | VCC | 2 | 5 | 6 | V | 5 | |
| Input voltage | VI | 0 | V | 5 | |||
| Output voltage | VO | 0 | V | 5 | |||
| Operating ambient temperature | Tamb | -40 | 85 | ℃ | 5 | ||
| Input rise and fall rate | Δt/ΔV | 625 | ns/V | VCC=2.0V | 5 | ||
| Input rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC=4.5V | 5 | |
| Input rise and fall rate | Δt/ΔV | 83 | ns/V | VCC=6.0V | 5 | ||
| High-level input voltage | VIH | 1.5 | V | VCC=2.0V; Tamb=-40~+85℃ | 6 | ||
| High-level input voltage | VIH | 3.15 | V | VCC=4.5V; Tamb=-40~+85℃ | 6 | ||
| High-level input voltage | VIH | 4.2 | V | VCC=6.0V; Tamb=-40~+85℃ | 6 | ||
| Low-level input voltage | VIL | 0.5 | V | VCC=2.0V; Tamb=-40~+85℃ | 6 | ||
| Low-level input voltage | VIL | 1.35 | V | VCC=4.5V; Tamb=-40~+85℃ | 6 | ||
| Low-level input voltage | VIL | 1.8 | V | VCC=6.0V; Tamb=-40~+85℃ | 6 | ||
| High-level output voltage | VOH | 1.9 | V | Vi=VIH or VIL; IO=-20uA; VCC=2.0V; Tamb=-40~+85℃ | 6 | ||
| High-level output voltage | VOH | 4.4 | V | Vi=VIH or VIL; IO=-20uA; VCC=4.5V; Tamb=-40~+85℃ | 6 | ||
| High-level output voltage | VOH | 5.9 | V | Vi=VIH or VIL; IO=-20uA; VCC=6.0V; Tamb=-40~+85℃ | 6 | ||
| High-level output voltage | VOH | 3.84 | V | Vi=VIH or VIL; IO=-4mA; VCC=4.5V; Tamb=-40~+85℃ | 6 | ||
| High-level output voltage | VOH | 5.34 | V | Vi=VIH or VIL; IO=-5.2mA; VCC=6.0V; Tamb=-40~+85℃ | 6 | ||
| Low-level output voltage | VOL | 0.1 | V | Vi=VIH or VIL; IO=20uA; VCC=2.0V; Tamb=-40~+85℃ | 6 | ||
| Low-level output voltage | VOL | 0.33 | V | Vi=VIH or VIL; IO=4mA; VCC=4.5V; Tamb=-40~+85℃ | 6 | ||
| Input leakage current | II | -1 | 1 | uA | VCC=6.0V; VI=VCC or GND; Tamb=-40~+85℃ | 6 | |
| Quiescent supply current | ICC | 80 | uA | VCC=6.0V; IO=0A; VI=VCC or GND; Tamb=-40~+85℃ | 6 | ||
| High-level output voltage | VOH | 1.9 | 2 | V | Tamb=25℃; Vi=VIH or VIL; IO=-20uA; VCC=2.0V | 5 | |
| High-level output voltage | VOH | 4.4 | 4.5 | V | Tamb=25℃; Vi=VIH or VIL; IO=-20uA; VCC=4.5V | 5 | |
| High-level output voltage | VOH | 5.9 | 6 | V | Tamb=25℃; Vi=VIH or VIL; IO=-20uA; VCC=6.0V | 5 | |
| High-level output voltage | VOH | 3.98 | 4.32 | V | Tamb=25℃; Vi=VIH or VIL; IO=-4.0mA; VCC=4.5V | 5 | |
| High-level output voltage | VOH | 5.48 | 5.81 | V | Tamb=25℃; Vi=VIH or VIL; IO=-5.2mA; VCC=6.0V | 5 | |
| Low-level output voltage | VOL | 0 | 0.1 | V | Tamb=25℃; Vi=VIH or VIL; IO=20uA; VCC=2.0V | 5 | |
| Low-level output voltage | VOL | 0.15 | 0.26 | V | Tamb=25℃; Vi=VIH or VIL; IO=4.0mA; VCC=4.5V | 5 | |
| Low-level output voltage | VOL | 0.16 | 0.26 | V | Tamb=25℃; Vi=VIH or VIL; IO=5.2mA; VCC=6.0V | 5 | |
| Input leakage current | II | -0.1 | 0.1 | uA | Tamb=25℃; VCC=6.0V; VI=VCC or GND | 5 | |
| Quiescent supply current | ICC | 8 | uA | Tamb=25℃; VCC=6.0V; IO=0A; VI=VCC or GND | 6 | ||
| CP to Qn propagation delay | tpd | 185 | ns | Tamb=-40~+85℃; VCC=2.0V; see Fig.5 | 7 | ||
| CP to Qn propagation delay | tpd | 37 | ns | Tamb=-40~+85℃; VCC=4.5V; see Fig.5 | 7 | ||
| CP to Qn propagation delay | tpd | 31 | ns | Tamb=-40~+85℃; VCC=6.0V; see Fig.5 | 7 | ||
| Dn to CP setup time | tsu | 75 | ns | Tamb=-40~+85℃; VCC=2.0V; see Fig.7 | 7 | ||
| Dn to CP setup time | tsu | 15 | ns | Tamb=-40~+85℃; VCC=4.5V; see Fig.7 | 7 | ||
| Dn to CP setup time | tsu | 13 | ns | Tamb=-40~+85℃; VCC=6.0V; see Fig.7 | 7 | ||
| CP input pulse width (high or low) | tW | 100 | ns | Tamb=-40~+85℃; VCC=2.0V; see Fig.5 | 7 | ||
| CP input pulse width (high or low) | tW | 20 | ns | Tamb=-40~+85℃; VCC=4.5V; see Fig.5 | 7 | ||
| CP input pulse width (high or low) | tW | 17 | ns | Tamb=-40~+85℃; VCC=6.0V; see Fig.5 | 7 | ||
| Maximum CP input frequency | fmax | 4.8 | MHz | Tamb=-40~+85℃; VCC=2.0V; see Fig.5 | 7 | ||
| Maximum CP input frequency | fmax | 24 | MHz | Tamb=-40~+85℃; VCC=4.5V; see Fig.5 | 7 | ||
| Maximum CP input frequency | fmax | 28 | MHz | Tamb=-40~+85℃; VCC=6.0V; see Fig.5 | 7 | ||
| CP to Qn propagation delay | tpd | 15 | 30 | ns | Tamb=25℃; VCC=4.5V; see Fig.5 | 6 | |
| Maximum CP input frequency | fmax | 30 | 103 | MHz | Tamb=25℃; VCC=4.5V; see Fig.5 | 7 |
CAD (KiCad official)
- Symbol:
74HC273M - Footprint:
Package_SO:SOP-20_7.5x12.8mm_P1.27mm - 3D model: SOP-20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
74hc273m-etched.step/74hc273m-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc273m.step/74hc273m.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HGSEMI datasheet (13 pp, sha256
7e8aa93a8f90838a, retrieved 2026-10-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).