component

74HC245PW

Public Made by Adom

by adom

Nexperia Buffer/Driver/Transceiver, TSSOP-20. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

componentlogic74hc245pw
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs 74hc245pw: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 2mo ago
74hc245pw-etched.fit.json 74hc245pw: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
74hc245pw-etched.glb 74hc245pw: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body w… · Ray 15d ago
74hc245pw-etched.step 74hc245pw: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body w… · Ray 15d ago
74hc245pw.glb Publish 0.1.0 · Ray 2mo ago
74hc245pw.kicad_mod Publish 0.1.0 · Ray 2mo ago
74hc245pw.kicad_sym Publish 0.1.0 · Ray 2mo ago
74hc245pw.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray 2mo ago
74hc245pw.step Publish 0.1.0 · Ray 2mo ago
package.json Publish 0.2.0 · Ray 2mo ago
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 2mo ago
page.json 74hc245pw: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body w… · Ray 15d ago
README.md 74hc245pw: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago

74HC245PW

Nexperia · Buffer/Driver/Transceiver · TSSOP-20

74HC245PW from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DIR input Direction control input. LOW routes data from Bn (input) to An (output); HIGH routes data from An (input) to Bn (output). CMOS-level input; VIH >= 0.7*VCC (74HC).
2 A0 tri_state Bidirectional data pin, port A bit 0. Acts as input when DIR=HIGH and as 3-state output when DIR=LOW (with OE=LOW). High-impedance when OE=HIGH.
3 A1 tri_state Bidirectional data pin, port A bit 1. Direction set by DIR; enabled by OE (active LOW).
4 A2 tri_state Bidirectional data pin, port A bit 2. Direction set by DIR; enabled by OE (active LOW).
5 A3 tri_state Bidirectional data pin, port A bit 3. Direction set by DIR; enabled by OE (active LOW).
6 A4 tri_state Bidirectional data pin, port A bit 4. Direction set by DIR; enabled by OE (active LOW).
7 A5 tri_state Bidirectional data pin, port A bit 5. Direction set by DIR; enabled by OE (active LOW).
8 A6 tri_state Bidirectional data pin, port A bit 6. Direction set by DIR; enabled by OE (active LOW).
9 A7 tri_state Bidirectional data pin, port A bit 7. Direction set by DIR; enabled by OE (active LOW).
10 GND power_in Ground reference (0 V). Absolute max ground current IGND = -70 mA.
11 B7 tri_state Bidirectional data pin, port B bit 7. Direction set by DIR (HIGH: An->Bn output, LOW: Bn input); enabled by OE (active LOW).
12 B6 tri_state Bidirectional data pin, port B bit 6. Direction set by DIR; enabled by OE (active LOW).
13 B5 tri_state Bidirectional data pin, port B bit 5. Direction set by DIR; enabled by OE (active LOW).
14 B4 tri_state Bidirectional data pin, port B bit 4. Direction set by DIR; enabled by OE (active LOW).
15 B3 tri_state Bidirectional data pin, port B bit 3. Direction set by DIR; enabled by OE (active LOW).
16 B2 tri_state Bidirectional data pin, port B bit 2. Direction set by DIR; enabled by OE (active LOW).
17 B1 tri_state Bidirectional data pin, port B bit 1. Direction set by DIR; enabled by OE (active LOW).
18 B0 tri_state Bidirectional data pin, port B bit 0. Direction set by DIR; enabled by OE (active LOW).
19 OE input Output enable, active LOW. LOW enables the transceiver (direction per DIR); HIGH forces both A and B ports to high-impedance OFF-state.
20 VCC power_in Positive supply voltage. 74HC245: 2.0 V to 6.0 V (recommended); absolute max 7 V. Recommended 4.5-5.5 V for 74HCT variant.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-20
Category Logic
Pins 20

Ordering variants

  • 74HC245PW
  • 74HC245PWD
  • 74HC245PWBQ

CAD (KiCad official)

  • Symbol: 74HC245PW
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: 74hc245pw-etched.step / 74hc245pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc245pw.step / 74hc245pw.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
74hc245pw.step 267 KB You want the bare part, or you mark your own boards.
74hc245pw-etched.step 2.3 MB You want the part with 74HC245PW already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 591 faces against 327 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (15 pp, sha256 ff2562c806a0fc87, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF