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74HC244PW-Q100

Public Made by Adom

by adom

Nexperia Buffers, Drivers, Receivers, Transceivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74HC244PW-Q100

Nexperia · Buffers, Drivers, Receivers, Transceivers · TSSOP-20

74HC244PW-Q100 from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Output enable input for outputs 1Y0 to 1Y3, active LOW; a HIGH on nOE forces the outputs into the high-impedance OFF-state.
2 1A0 input Data input of the first 4-bit buffer; the 74HC244-Q100 uses CMOS input levels and the 74HCT244-Q100 uses TTL input levels, and clamp diodes allow current-limiting resistors for inputs above VCC.
3 2Y0 tri_state Non-inverting 3-state bus output of the second 4-bit buffer, high-impedance when 2OE is HIGH.
4 1A1 input Data input of the first 4-bit buffer; the 74HC244-Q100 uses CMOS input levels and the 74HCT244-Q100 uses TTL input levels, and clamp diodes allow current-limiting resistors for inputs above VCC.
5 2Y1 tri_state Non-inverting 3-state bus output of the second 4-bit buffer, high-impedance when 2OE is HIGH.
6 1A2 input Data input of the first 4-bit buffer; the 74HC244-Q100 uses CMOS input levels and the 74HCT244-Q100 uses TTL input levels, and clamp diodes allow current-limiting resistors for inputs above VCC.
7 2Y2 tri_state Non-inverting 3-state bus output of the second 4-bit buffer, high-impedance when 2OE is HIGH.
8 1A3 input Data input of the first 4-bit buffer; the 74HC244-Q100 uses CMOS input levels and the 74HCT244-Q100 uses TTL input levels, and clamp diodes allow current-limiting resistors for inputs above VCC.
9 2Y3 tri_state Non-inverting 3-state bus output of the second 4-bit buffer, high-impedance when 2OE is HIGH.
10 GND power_in Ground (0 V) reference for all voltages on the device.
11 2A3 input Data input of the second 4-bit buffer; the 74HC244-Q100 uses CMOS input levels and the 74HCT244-Q100 uses TTL input levels, and clamp diodes allow current-limiting resistors for inputs above VCC.
12 1Y3 tri_state Non-inverting 3-state bus output of the first 4-bit buffer, high-impedance when 1OE is HIGH.
13 2A2 input Data input of the second 4-bit buffer; the 74HC244-Q100 uses CMOS input levels and the 74HCT244-Q100 uses TTL input levels, and clamp diodes allow current-limiting resistors for inputs above VCC.
14 1Y2 tri_state Non-inverting 3-state bus output of the first 4-bit buffer, high-impedance when 1OE is HIGH.
15 2A1 input Data input of the second 4-bit buffer; the 74HC244-Q100 uses CMOS input levels and the 74HCT244-Q100 uses TTL input levels, and clamp diodes allow current-limiting resistors for inputs above VCC.
16 1Y1 tri_state Non-inverting 3-state bus output of the first 4-bit buffer, high-impedance when 1OE is HIGH.
17 2A0 input Data input of the second 4-bit buffer; the 74HC244-Q100 uses CMOS input levels and the 74HCT244-Q100 uses TTL input levels, and clamp diodes allow current-limiting resistors for inputs above VCC.
18 1Y0 tri_state Non-inverting 3-state bus output of the first 4-bit buffer, high-impedance when 1OE is HIGH.
19 2OE input Output enable input for outputs 2Y0 to 2Y3, active LOW; a HIGH on nOE forces the outputs into the high-impedance OFF-state.
20 VCC power_in Supply voltage: 2.0 V to 6.0 V for 74HC244-Q100 and 4.5 V to 5.5 V for 74HCT244-Q100, with an absolute maximum of +7 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 7 V 4
input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 4
output current IO -35 35 mA -0.5 V < VO < VCC + 0.5 V 4
supply current ICC 70 mA 4
ground current IGND -70 mA 4
storage temperature Tstg -65 150 °C 4
total power dissipation Ptot 500 mW SOT360-1 (TSSOP20): derates linearly with 10.0 mW/K above 100 °C 4
supply voltage (74HC244-Q100) VCC 2 5 6 V 4
input voltage VI 0 V maximum printed as VCC 4
output voltage VO 0 V maximum printed as VCC 4
input transition rise and fall rate Δt/ΔV 625 ns/V VCC = 2.0 V 4
input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 4
input transition rise and fall rate Δt/ΔV 83 ns/V VCC = 6.0 V 4
ambient temperature Tamb -40 125 °C 4
HIGH-level input voltage VIH 1.5 1.2 V -40 °C to +125 °C; VCC = 2.0 V 5
HIGH-level input voltage VIH 3.15 2.4 V -40 °C to +125 °C; VCC = 4.5 V 5
HIGH-level input voltage VIH 4.2 3.2 V -40 °C to +125 °C; VCC = 6.0 V 5
LOW-level input voltage VIL 0.8 0.5 V -40 °C to +125 °C; VCC = 2.0 V 5
LOW-level input voltage VIL 2.1 1.35 V -40 °C to +125 °C; VCC = 4.5 V 5
LOW-level input voltage VIL 2.8 1.8 V -40 °C to +125 °C; VCC = 6.0 V 5
HIGH-level output voltage VOH 1.9 2 V VI = VIH or VIL; IO = -20 μA; VCC = 2.0 V; -40 °C to +125 °C 5
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V; -40 °C to +125 °C 5
HIGH-level output voltage VOH 5.9 6 V VI = VIH or VIL; IO = -20 μA; VCC = 6.0 V; -40 °C to +125 °C 5
HIGH-level output voltage VOH 3.7 4.32 V VI = VIH or VIL; IO = -6.0 mA; VCC = 4.5 V; -40 °C to +125 °C 5
HIGH-level output voltage VOH 5.2 5.81 V VI = VIH or VIL; IO = -7.8 mA; VCC = 6.0 V; -40 °C to +125 °C 5
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V; -40 °C to +125 °C 5
LOW-level output voltage VOL 0.15 0.4 V VI = VIH or VIL; IO = 6.0 mA; VCC = 4.5 V; -40 °C to +125 °C 5
LOW-level output voltage VOL 0.16 0.4 V VI = VIH or VIL; IO = 7.8 mA; VCC = 6.0 V; -40 °C to +125 °C 5
input leakage current II -1 1 μA VI = VCC or GND; VCC = 6.0 V; -40 °C to +125 °C 5
OFF-state output current IOZ -10 10 μA VI = VIH or VIL; VCC = 6.0 V; VO = VCC or GND; -40 °C to +125 °C 5
supply current ICC 160 μA VI = VCC or GND; IO = 0 A; VCC = 6.0 V; -40 °C to +125 °C 5
propagation delay nAn to nYn tpd 30 165 ns nAn to nYn; see Fig. 6; VCC = 2.0 V; -40 °C to +125 °C 7
propagation delay nAn to nYn tpd 11 33 ns nAn to nYn; see Fig. 6; VCC = 4.5 V; -40 °C to +125 °C 7
propagation delay nAn to nYn tpd 9 28 ns nAn to nYn; see Fig. 6; VCC = 6.0 V; -40 °C to +125 °C 7
enable time nOE to nYn ten 36 225 ns nOE to nYn; see Fig. 7; VCC = 2.0 V; -40 °C to +125 °C 7
enable time nOE to nYn ten 13 45 ns nOE to nYn; see Fig. 7; VCC = 4.5 V; -40 °C to +125 °C 7
enable time nOE to nYn ten 10 38 ns nOE to nYn; see Fig. 7; VCC = 6.0 V; -40 °C to +125 °C 7
disable time nOE to nYn tdis 39 225 ns nOE to nYn; see Fig. 7; VCC = 2.0 V; -40 °C to +125 °C 7
disable time nOE to nYn tdis 14 45 ns nOE to nYn; see Fig. 7; VCC = 4.5 V; -40 °C to +125 °C 7
disable time nOE to nYn tdis 11 38 ns nOE to nYn; see Fig. 7; VCC = 6.0 V; -40 °C to +125 °C 7
transition time tt 14 90 ns see Fig. 6; VCC = 2.0 V; -40 °C to +125 °C 7
transition time tt 5 18 ns see Fig. 6; VCC = 4.5 V; -40 °C to +125 °C 7
transition time tt 4 15 ns see Fig. 6; VCC = 6.0 V; -40 °C to +125 °C 7

CAD (KiCad official)

  • Symbol: 74HC244PW-Q100
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: 74hc244pw-q100-etched.step / 74hc244pw-q100-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc244pw-q100.step / 74hc244pw-q100.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (15 pp, sha256 0ffd603f545a1af8, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF