# 74HC1G08GW

**Nexperia** · Logic Gates · SOT-353

74HC1G08GW from Nexperia, in a SOT-353. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | B | input | Data input B of the 2-input AND gate; the recommended input voltage range is 0 V to VCC. |
| 2 | A | input | Data input A of the 2-input AND gate; the recommended input voltage range is 0 V to VCC. |
| 3 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 4 | Y | output | Data output of the AND gate; the recommended output voltage range is 0 V to VCC. |
| 5 | VCC | power_in | Supply voltage: recommended 2.0 V to 6.0 V for 74HC1G08, with a absolute maximum of 7.0 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOT-353 |
| Category | Logic |
| Pins | 5 |

## CAD (KiCad official)

- Symbol: `74HC1G08GW`
- Footprint: `Package_TO_SOT_SMD:SOT-353_SC-70-5`
- 3D model: SOT-353 (KiCad packages3D, STEP)
- 3D model files: `74hc1g08gw-etched.step` / `74hc1g08gw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74hc1g08gw.step` / `74hc1g08gw.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Nexperia datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586172405589430272) (12 pp, sha256 `2fe2aeb4ebfb429f`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/74hc1g08gw-datasheet.pdf)