main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 20d ago
viewers 74hc1g00gw: viewers · Ray 20d ago
74hc1g00gw-etched.glb 74hc1g00gw: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray 8d ago
74hc1g00gw-etched.step 74hc1g00gw: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray 8d ago
74hc1g00gw-hero.glb 74hc1g00gw: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray 8d ago
74hc1g00gw-hero.overlay.json 74hc1g00gw: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray 8d ago
74hc1g00gw.glb Publish 0.1.0 · Ray 20d ago
74hc1g00gw.kicad_mod Publish 0.1.0 · Ray 20d ago
74hc1g00gw.kicad_sym Publish 0.1.0 · Ray 20d ago
74hc1g00gw.lbr Publish 0.1.0 · Ray 20d ago
74hc1g00gw.step Publish 0.1.0 · Ray 20d ago
package.json 74hc1g00gw: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray 8d ago
page.json 74hc1g00gw: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray 8d ago
README.md Publish 0.1.0 · Ray 20d ago

74HC1G00GW

Nexperia · Logic Gates · SOT-353

74HC1G00GW from Nexperia, in a SOT-353. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 B input Data input B of the 2-input NAND gate; input voltage range is 0 V to VCC, and the datasheet gives CMOS input levels for 74HC1G00 (TTL levels for 74HCT1G00).
2 A input Data input A of the 2-input NAND gate; input voltage range is 0 V to VCC, and input clamp current is limited to ±20 mA when VI is below -0.5 V or above VCC + 0.5 V.
3 GND power_in Ground (0 V) reference; all voltage ratings in the datasheet are referenced to GND.
4 Y output Data output of the NAND gate; output voltage range is 0 V to VCC and output current is limited to ±12.5 mA.
5 VCC power_in Supply voltage; recommended range is 2.0 V to 6.0 V for 74HC1G00 (4.5 V to 5.5 V for 74HCT1G00), with an absolute maximum of 7.0 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOT-353
Category Logic
Pins 5

CAD (KiCad official)

  • Symbol: 74HC1G00GW
  • Footprint: Package_TO_SOT_SMD:SOT-353_SC-70-5
  • 3D model: SOT-353 (KiCad packages3D, STEP)
  • 3D model files: 74hc1g00gw-etched.step / 74hc1g00gw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc1g00gw.step / 74hc1g00gw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (10 pp, sha256 0a640db935c849ec, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF