# 74HC193M

**HGSEMI** · Counters, Dividers · SOP-16

74HC193M from HGSEMI, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | B | input | Data input B (preset input), loaded into its counter stage when LOAD is low; unused inputs must be held at VCC or GND. |
| 2 | QB | output | Counter flip-flop output QB, forced low when CLR is high and drives up to 10 LSTTL loads. |
| 3 | QA | output | Counter flip-flop output QA, forced low when CLR is high and drives up to 10 LSTTL loads. |
| 4 | DOWN | input | Count-down clock input, triggers on a low-to-high transition while UP is held high. |
| 5 | UP | input | Count-up clock input, triggers on a low-to-high transition while DOWN is held high. |
| 6 | QC | output | Counter flip-flop output QC, forced low when CLR is high and drives up to 10 LSTTL loads. |
| 7 | QD | output | Counter flip-flop output QD, forced low when CLR is high and drives up to 10 LSTTL loads. |
| 8 | GND | power_in | Ground reference (0 V) for the device. |
| 9 | D | input | Data input D (preset input), loaded into its counter stage when LOAD is low. |
| 10 | C | input | Data input C (preset input), loaded into its counter stage when LOAD is low. |
| 11 | LOAD | input | Active-low asynchronous parallel load input that presets the outputs to the data inputs independently of the count pulses. |
| 12 | CO | output | Active-low carry output that pulses low while the count is maximum (9 or 15) and UP is low, feeding UP of the next stage. |
| 13 | BO | output | Active-low borrow output that pulses low while the count is zero and DOWN is low, feeding DOWN of the next stage. |
| 14 | CLR | input | Asynchronous clear input that forces all outputs low when high, independent of the count and LOAD inputs. |
| 15 | A | input | Data input A (preset input), loaded into its counter stage when LOAD is low. |
| 16 | VCC | power_in | Supply voltage pin, recommended 2 V to 6 V (absolute maximum 7 V). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | HGSEMI |
| Package | SOP-16 |
| Category | Logic |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 2 | 5 | 6 | V |  | 5 |
| High-level input voltage | VIH | 1.5 |  |  | V | VCC = 2 V | 5 |
| High-level input voltage | VIH | 3.15 |  |  | V | VCC = 4.5 V | 5 |
| High-level input voltage | VIH | 4.2 |  |  | V | VCC = 6 V | 5 |
| Low-level input voltage | VIL |  |  | 0.5 | V | VCC = 2 V | 5 |
| Low-level input voltage | VIL |  |  | 1.35 | V | VCC = 4.5 V | 5 |
| Low-level input voltage | VIL |  |  | 1.8 | V | VCC = 6 V | 5 |
| Input voltage | VI | 0 |  |  | V |  | 5 |
| Output voltage | VO | 0 |  |  | V |  | 5 |
| Input transition rise/fall time | t/∆v |  |  | 1000 | ns | VCC = 2 V | 5 |
| Input transition rise/fall time | t/∆v |  |  | 500 | ns | VCC = 4.5 V | 5 |
| Input transition rise/fall time | t/∆v |  |  | 400 | ns | VCC = 6 V | 5 |
| Operating free-air temperature | TA | -40 |  | 85 | °C |  | 5 |
| Supply voltage range | VCC | -0.5 |  | 7 | V |  | 5 |
| Input clamp current | IIK | -20 |  | 20 | mA | VI<0 or VI>VCC (see Note 1) | 5 |
| Output clamp current | IO | -20 |  | 20 | mA | Vo<0 or Vo>VCC (see Note 1) | 5 |
| Continuous output current | IO | -25 |  | 25 | mA | VO = 0 to VCC | 5 |
| Continuous current through VCC or GND |  | -50 |  | 50 | mA |  | 5 |
| Package thermal impedance, M package | θJA |  | 73 |  | °C/W | M package (see Note 2) | 5 |
| Storage temperature range | Tstg | -65 |  | 150 | °C |  | 5 |
| High-level output voltage | VOH | 1.9 | 1.998 |  | V | VI = VIH or VIL; IOH = −20 A; VCC = 2 V | 6 |
| High-level output voltage | VOH | 4.4 | 4.499 |  | V | VI = VIH or VIL; IOH = −20 A; VCC = 4.5 V | 6 |
| High-level output voltage | VOH | 5.9 | 5.999 |  | V | VI = VIH or VIL; IOH = −20 A; VCC = 6 V | 6 |
| High-level output voltage | VOH | 3.84 | 4.3 |  | V | VI = VIH or VIL; IOH = −4 mA; VCC = 4.5 V | 6 |
| High-level output voltage | VOH | 5.34 | 5.8 |  | V | VI = VIH or VIL; IOH = −5.2 mA; VCC = 6 V | 6 |
| Low-level output voltage | VOL |  | 0.002 | 0.1 | V | VI = VIH or VIL; IOL = 20 A; VCC = 2 V | 6 |
| Low-level output voltage | VOL |  | 0 | 0.1 | V | VI = VIH or VIL; IOL = 20 A; VCC = 4.5 V | 6 |
| Low-level output voltage | VOL |  | 0.001 | 0.1 | V | VI = VIH or VIL; IOL = 20 A; VCC = 6 V | 6 |
| Low-level output voltage | VOL |  | 0.17 | 0.33 | V | VI = VIH or VIL; IOL = 4 mA; VCC = 4.5 V | 6 |
| Low-level output voltage | VOL |  | 0.15 | 0.33 | V | VI = VIH or VIL; IOL = 5.2 mA; VCC = 6 V | 6 |
| Input current | II | -1000 | 0.1 | 1000 | nA | VI = VCC or 0; VCC = 6 V | 6 |
| Supply current | ICC |  | 8 | 80 | µA | VI = VCC or 0, IO = 0; VCC = 6 V | 6 |
| Input capacitance | Ci |  | 3 | 10 | pF | VCC = 2 V to 6 V | 6 |
| Clock frequency | fclock | 3.3 |  |  | MHz | VCC = 2 V | 6 |
| Clock frequency | fclock | 17 |  |  | MHz | VCC = 4.5 V | 6 |
| Clock frequency | fclock | 19 |  |  | MHz | VCC = 6 V | 6 |
| Pulse duration CLR high | tw | 150 |  |  | ns | VCC = 2 V | 6 |
| Pulse duration CLR high | tw | 30 |  |  | ns | VCC = 4.5 V | 6 |
| Pulse duration CLR high | tw | 26 |  |  | ns | VCC = 6 V | 6 |
| Pulse duration LOAD low | tw | 150 |  |  | ns | VCC = 2 V | 6 |
| Pulse duration LOAD low | tw | 30 |  |  | ns | VCC = 4.5 V | 6 |
| Pulse duration LOAD low | tw | 26 |  |  | ns | VCC = 6 V | 6 |
| Pulse duration UP or DOWN high or low | tw | 150 |  |  | ns | VCC = 2 V | 6 |
| Pulse duration UP or DOWN high or low | tw | 30 |  |  | ns | VCC = 4.5 V | 6 |
| Pulse duration UP or DOWN high or low | tw | 26 |  |  | ns | VCC = 6 V | 6 |
| Setup time data before LOAD inactive | tsu | 140 |  |  | ns | VCC = 2 V | 6 |
| Setup time data before LOAD inactive | tsu | 28 |  |  | ns | VCC = 4.5 V | 6 |
| Setup time data before LOAD inactive | tsu | 24 |  |  | ns | VCC = 6 V | 6 |
| Setup time CLR inactive before UP↑ or DOWN | tsu | 140 |  |  | ns | VCC = 2 V | 6 |
| Setup time CLR inactive before UP↑ or DOWN | tsu | 28 |  |  | ns | VCC = 4.5 V | 6 |
| Setup time CLR inactive before UP↑ or DOWN | tsu | 24 |  |  | ns | VCC = 6 V | 6 |
| Setup time LOAD inactive before UP↑ or DOWN | tsu | 140 |  |  | ns | VCC = 2 V | 6 |
| Setup time LOAD inactive before UP↑ or DOWN | tsu | 28 |  |  | ns | VCC = 4.5 V | 6 |
| Setup time LOAD inactive before UP↑ or DOWN | tsu | 24 |  |  | ns | VCC = 6 V | 6 |
| Hold time data after LOAD inactive | th | 5 |  |  | ns | VCC = 2 V | 6 |

## CAD (KiCad official)

- Symbol: `74HC193M`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files: `74hc193m-etched.step` / `74hc193m-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74hc193m.step` / `74hc193m.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [HGSEMI datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603087547749060608) (11 pp, sha256 `034488b36d5ee7df`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/74hc193m-datasheet.pdf)