component

74HC175PW

Public Made by Adom

by adom

Nexperia Flip Flops, TSSOP-16. Pinout settled in review by an AI reviewer against the manufacturer's datasheet, KiCad symbol/footprint/3D.

componentlogic74hc175pwfactory-2.0.0extractor-text

Verified 74HC175PW

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: 74HC175PW · TSSOP-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 16-page datasheet
  • •distributor (warn): no ['digikey'] number
  • ✓family: TSSOP-16_4.4x5mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-huh286gq/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.13)
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ 74hc175pw.kicad_sym✓ 74hc175pw.kicad_mod✓ 74hc175pw.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 2h ago
viewers 74hc175pw: viewers after the pinout correction · Ray 2h ago
74hc175pw-etched.glb Publish 0.1.0 · Ray 2h ago
74hc175pw-etched.step 74hc175pw: factory component page (tier=mfr) · Ray 2h ago
74hc175pw-hero.glb Publish 0.1.1 · Ray 2h ago
74hc175pw-hero.overlay.json Publish 0.1.1 · Ray 2h ago
74hc175pw.glb Publish 0.1.0 · Ray 2h ago
74hc175pw.kicad_mod Publish 0.1.0 · Ray 2h ago
74hc175pw.kicad_sym Publish 0.1.1 · Ray 2h ago
74hc175pw.lbr Publish 0.1.1 · Ray 2h ago
74hc175pw.step Publish 0.1.0 · Ray 2h ago
package.json Publish 0.1.1 · Ray 2h ago
page.json brief: say who settled the pinout (an AI reviewer or models), not a person · Ray 2h ago
README.md Publish 0.1.1 · Ray 2h ago
verification.json Verified: Published by the parts factory: tier mfr, 16 pins · Ray 2h ago

74HC175PW

Nexperia · Flip Flops · TSSOP-16

74HC175PW from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ~{MR} input Asynchronous master reset input (active LOW) that resets all flip-flops and outputs LOW.
2 Q0 output Flip-flop 0 output.
3 ~{Q0} output Complementary flip-flop 0 output.
4 D0 input Data input for flip-flop 0, stored on the LOW-to-HIGH clock transition when set-up and hold times are met.
5 D1 input Data input for flip-flop 1, stored on the LOW-to-HIGH clock transition when set-up and hold times are met.
6 ~{Q1} output Complementary flip-flop 1 output.
7 Q1 output Flip-flop 1 output.
8 GND power_in Ground (0 V).
9 CP input Clock input, positive (LOW-to-HIGH) edge-triggered.
10 Q2 output Flip-flop 2 output.
11 ~{Q2} output Complementary flip-flop 2 output.
12 D2 input Data input for flip-flop 2, stored on the LOW-to-HIGH clock transition when set-up and hold times are met.
13 D3 input Data input for flip-flop 3, stored on the LOW-to-HIGH clock transition when set-up and hold times are met.
14 ~{Q3} output Complementary flip-flop 3 output.
15 Q3 output Flip-flop 3 output.
16 VCC power_in Positive supply voltage; 2.0 V to 6.0 V for 74HC175 and 4.5 V to 5.5 V for 74HCT175 per recommended operating conditions.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage (absolute maximum) VCC -0.5 7 V 4
input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 4
output current IO -25 25 mA -0.5 V < VO < VCC + 0.5 V 4
supply current ICC 50 mA 4
ground current IGND -50 mA 4
storage temperature Tstg -65 150 °C 4
total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 4
supply voltage VCC 2 5 6 V 4
input voltage VI 0 V 4
output voltage VO 0 V 4
ambient temperature Tamb -40 125 °C 4
input transition rise and fall rate Δt/ΔV 625 ns/V VCC = 2.0 V 4
input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 4
input transition rise and fall rate Δt/ΔV 83 ns/V VCC = 6.0 V 4
HIGH-level input voltage VIH 1.5 V VCC = 2.0 V; -40 °C to +125 °C 5
HIGH-level input voltage VIH 3.15 V VCC = 4.5 V; -40 °C to +125 °C 5
HIGH-level input voltage VIH 4.2 V VCC = 6.0 V; -40 °C to +125 °C 5
LOW-level input voltage VIL 0.5 V VCC = 2.0 V; -40 °C to +125 °C 5
LOW-level input voltage VIL 1.35 V VCC = 4.5 V; -40 °C to +125 °C 5
LOW-level input voltage VIL 1.8 V VCC = 6.0 V; -40 °C to +125 °C 5
HIGH-level output voltage VOH 1.9 V VI = VIH or VIL; IO = -20 μA; VCC = 2.0 V; -40 °C to +125 °C 5
HIGH-level output voltage VOH 4.4 V VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V; -40 °C to +125 °C 5
HIGH-level output voltage VOH 5.9 V VI = VIH or VIL; IO = -20 μA; VCC = 6.0 V; -40 °C to +125 °C 5
HIGH-level output voltage VOH 3.7 V VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V; -40 °C to +125 °C 5
HIGH-level output voltage VOH 5.2 V VI = VIH or VIL; IO = -5.2 mA; VCC = 6.0 V; -40 °C to +125 °C 5
LOW-level output voltage VOL 0.1 V VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V; -40 °C to +125 °C 5
LOW-level output voltage VOL 0.4 V VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V; -40 °C to +125 °C 5
input leakage current II -1 1 μA VI = VCC or GND; VCC = 6.0 V; -40 °C to +125 °C 5
supply current ICC 160 μA VI = VCC or GND; IO = 0 A; VCC = 6.0 V; -40 °C to +125 °C 5
propagation delay CP to Qn, Qn (tpd) tpd 265 ns CP to Qn, Qn; see Fig. 7; CL = 50 pF; VCC = 2.0 V; -40 °C to +125 °C 6
propagation delay CP to Qn, Qn (tpd) tpd 53 ns CP to Qn, Qn; see Fig. 7; CL = 50 pF; VCC = 4.5 V; -40 °C to +125 °C 6
propagation delay CP to Qn, Qn (tpd) tpd 45 ns CP to Qn, Qn; see Fig. 7; CL = 50 pF; VCC = 6.0 V; -40 °C to +125 °C 6
HIGH to LOW propagation delay MR to Qn, Qn (tPHL) tPHL 225 ns MR to Qn, Qn; see Fig. 8; CL = 50 pF; VCC = 2.0 V; -40 °C to +125 °C 6
HIGH to LOW propagation delay MR to Qn, Qn (tPHL) tPHL 45 ns MR to Qn, Qn; see Fig. 8; CL = 50 pF; VCC = 4.5 V; -40 °C to +125 °C 6
HIGH to LOW propagation delay MR to Qn, Qn (tPHL) tPHL 38 ns MR to Qn, Qn; see Fig. 8; CL = 50 pF; VCC = 6.0 V; -40 °C to +125 °C 6
transition time Qn output (tt) tt 110 ns Qn output; see Fig. 7; CL = 50 pF; VCC = 2.0 V; -40 °C to +125 °C 7
transition time Qn output (tt) tt 22 ns Qn output; see Fig. 7; CL = 50 pF; VCC = 4.5 V; -40 °C to +125 °C 7
transition time Qn output (tt) tt 19 ns Qn output; see Fig. 7; CL = 50 pF; VCC = 6.0 V; -40 °C to +125 °C 7
pulse width CP input HIGH or LOW (tW) tW 120 ns CP input HIGH or LOW; see Fig. 7; VCC = 2.0 V; -40 °C to +125 °C 7
pulse width CP input HIGH or LOW (tW) tW 24 ns CP input HIGH or LOW; see Fig. 7; VCC = 4.5 V; -40 °C to +125 °C 7
pulse width CP input HIGH or LOW (tW) tW 20 ns CP input HIGH or LOW; see Fig. 7; VCC = 6.0 V; -40 °C to +125 °C 7
pulse width MR input LOW (tW) tW 120 ns MR input LOW; see Fig. 8; VCC = 2.0 V; -40 °C to +125 °C 7
pulse width MR input LOW (tW) tW 24 ns MR input LOW; see Fig. 8; VCC = 4.5 V; -40 °C to +125 °C 7
pulse width MR input LOW (tW) tW 20 ns MR input LOW; see Fig. 8; VCC = 6.0 V; -40 °C to +125 °C 7
recovery time MR to CP (trec) trec 5 ns MR to CP; see Fig. 8; VCC = 2.0 V; -40 °C to +125 °C 7
set-up time Dn to CP (tsu) tsu 120 ns Dn to CP; see Fig. 9; VCC = 2.0 V; -40 °C to +125 °C 7
set-up time Dn to CP (tsu) tsu 24 ns Dn to CP; see Fig. 9; VCC = 4.5 V; -40 °C to +125 °C 7
set-up time Dn to CP (tsu) tsu 20 ns Dn to CP; see Fig. 9; VCC = 6.0 V; -40 °C to +125 °C 7
hold time Dn to CP (th) th 40 ns Dn to CP; see Fig. 9; VCC = 2.0 V; -40 °C to +125 °C 7
hold time Dn to CP (th) th 8 ns Dn to CP; see Fig. 9; VCC = 4.5 V; -40 °C to +125 °C 7
hold time Dn to CP (th) th 7 ns Dn to CP; see Fig. 9; VCC = 6.0 V; -40 °C to +125 °C 7
maximum frequency CP input (fmax) fmax 4 MHz CP input; see Fig. 7; VCC = 2.0 V; -40 °C to +125 °C 7
maximum frequency CP input (fmax) fmax 20 MHz CP input; see Fig. 7; VCC = 4.5 V; -40 °C to +125 °C 7
maximum frequency CP input (fmax) fmax 24 MHz CP input; see Fig. 7; VCC = 6.0 V; -40 °C to +125 °C 7

CAD (KiCad official)

  • Symbol: 74HC175PW
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: 74hc175pw-etched.step / 74hc175pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc175pw.step / 74hc175pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (16 pp, sha256 374969b89f1ce8c5, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF