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74HC175D

Public Made by Adom

by adom

Nexperia Flip Flops, SOIC-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs 74hc175d: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers 74hc175d: viewers · Ray 2mo ago
74hc175d-etched.fit.json 74hc175d: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
74hc175d-etched.glb 74hc175d: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body wi… · Ray 13d ago
74hc175d-etched.step 74hc175d: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body wi… · Ray 13d ago
74hc175d.glb Publish 0.1.0 · Ray 2mo ago
74hc175d.kicad_mod Publish 0.1.0 · Ray 2mo ago
74hc175d.kicad_sym Publish 0.1.0 · Ray 2mo ago
74hc175d.lbr Publish 0.1.0 · Ray 2mo ago
74hc175d.step Publish 0.1.0 · Ray 2mo ago
package.json Publish 0.1.0 · Ray 2mo ago
page.json 74hc175d: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body wi… · Ray 13d ago
README.md 74hc175d: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago

74HC175D

Nexperia · Flip Flops · SOIC-16

74HC175D from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MR input Asynchronous master reset input, active LOW. Driving MR LOW forces all four Q outputs LOW and all Q-bar outputs HIGH independently of the clock.
2 Q0 output True (non-inverting) flip-flop output for channel 0. Reflects the stored D0 value after a LOW-to-HIGH CP edge.
3 Q0_N output Complementary (inverted) flip-flop output for channel 0.
4 D0 input Data input for flip-flop 0. Sampled on the LOW-to-HIGH transition of CP subject to setup/hold timing.
5 D1 input Data input for flip-flop 1. Sampled on the LOW-to-HIGH transition of CP.
6 Q1_N output Complementary (inverted) flip-flop output for channel 1.
7 Q1 output True (non-inverting) flip-flop output for channel 1.
8 GND power_in Ground reference (0 V).
9 CP input Common clock input, positive-edge triggered. All four flip-flops latch their D inputs on the LOW-to-HIGH transition.
10 Q2 output True (non-inverting) flip-flop output for channel 2.
11 Q2_N output Complementary (inverted) flip-flop output for channel 2.
12 D2 input Data input for flip-flop 2. Sampled on the LOW-to-HIGH transition of CP.
13 D3 input Data input for flip-flop 3. Sampled on the LOW-to-HIGH transition of CP.
14 Q3_N output Complementary (inverted) flip-flop output for channel 3.
15 Q3 output True (non-inverting) flip-flop output for channel 3.
16 VCC power_in Positive supply voltage. 2.0 V to 6.0 V for 74HC175; 4.5 V to 5.5 V for 74HCT175.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOIC-16
Category Logic
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • 74HC175DD
  • 74HC175DPW

CAD (KiCad official)

  • Symbol: 74HC175D
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: 74hc175d-etched.step / 74hc175d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc175d.step / 74hc175d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (16 pp, sha256 374969b89f1ce8c5, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF