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74HC174PW

Public Made by Adom

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Nexperia Flip Flops, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74HC174PW

Nexperia · Flip Flops · TSSOP-16

74HC174PW from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MR input Asynchronous master reset input (active LOW); a LOW resets all flip-flops and Q outputs to LOW independent of the clock.
2 Q0 output Flip-flop 0 output; it follows D0 on the LOW-to-HIGH CP transition and is forced LOW by MR.
3 D0 input Data input for flip-flop 0; the level must meet set-up and hold times around the LOW-to-HIGH clock transition to be stored.
4 D1 input Data input for flip-flop 1; the level must meet set-up and hold times around the LOW-to-HIGH clock transition to be stored.
5 Q1 output Flip-flop 1 output; it follows D1 on the LOW-to-HIGH CP transition and is forced LOW by MR.
6 D2 input Data input for flip-flop 2; the level must meet set-up and hold times around the LOW-to-HIGH clock transition to be stored.
7 Q2 output Flip-flop 2 output; it follows D2 on the LOW-to-HIGH CP transition and is forced LOW by MR.
8 GND power_in Ground (0 V) reference for all voltages.
9 CP input Clock input; flip-flops load Dn on the LOW-to-HIGH edge.
10 Q3 output Flip-flop 3 output; it follows D3 on the LOW-to-HIGH CP transition and is forced LOW by MR.
11 D3 input Data input for flip-flop 3; the level must meet set-up and hold times around the LOW-to-HIGH clock transition to be stored.
12 Q4 output Flip-flop 4 output; it follows D4 on the LOW-to-HIGH CP transition and is forced LOW by MR.
13 D4 input Data input for flip-flop 4; the level must meet set-up and hold times around the LOW-to-HIGH clock transition to be stored.
14 D5 input Data input for flip-flop 5; the level must meet set-up and hold times around the LOW-to-HIGH clock transition to be stored.
15 Q5 output Flip-flop 5 output; it follows D5 on the LOW-to-HIGH CP transition and is forced LOW by MR.
16 VCC power_in Positive supply voltage; 2.0 V to 6.0 V for 74HC174 and 4.5 V to 5.5 V for 74HCT174 per the recommended operating conditions.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC supply voltage VCC -0.5 7 V 3
input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 3
output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 3
output current IO -25 25 mA -0.5 V < VO < VCC + 0.5 V 3
supply current ICC 50 mA 3
ground current IGND -50 mA 3
storage temperature Tstg -65 150 °C 3
total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 3
supply voltage VCC 2 5 6 V 4
input voltage VI 0 V 4
output voltage VO 0 V 4
ambient temperature Tamb -40 125 °C 4
input transition rise and fall rate Δt/ΔV 625 ns/V VCC = 2.0 V 4
input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 4
input transition rise and fall rate Δt/ΔV 83 ns/V VCC = 6.0 V 4
HIGH-level input voltage VIH 1.5 1.2 V VCC = 2.0 V; min at -40 °C to +125 °C 4
HIGH-level input voltage VIH 3.15 2.4 V VCC = 4.5 V; min at -40 °C to +125 °C 4
HIGH-level input voltage VIH 4.2 3.2 V VCC = 6.0 V; min at -40 °C to +125 °C 4
LOW-level input voltage VIL 0.8 0.5 V VCC = 2.0 V; max at -40 °C to +125 °C 4
LOW-level input voltage VIL 2.1 1.35 V VCC = 4.5 V; max at -40 °C to +125 °C 4
LOW-level input voltage VIL 2.8 1.8 V VCC = 6.0 V; max at -40 °C to +125 °C 4
HIGH-level output voltage VOH 1.9 2 V VI = VIH or VIL; IO = -20 μA; VCC = 2.0 V; min at -40 °C to +125 °C 4
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V; min at -40 °C to +125 °C 4
HIGH-level output voltage VOH 5.9 6 V VI = VIH or VIL; IO = -20 μA; VCC = 6.0 V; min at -40 °C to +125 °C 4
HIGH-level output voltage VOH 3.7 4.32 V VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V; min at -40 °C to +125 °C 4
HIGH-level output voltage VOH 5.2 5.81 V VI = VIH or VIL; IO = -5.2 mA; VCC = 6.0 V; min at -40 °C to +125 °C 4
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V; max at -40 °C to +125 °C 4
LOW-level output voltage VOL 0.15 0.4 V VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V; max at -40 °C to +125 °C 4
LOW-level output voltage VOL 0.16 0.4 V VI = VIH or VIL; IO = 5.2 mA; VCC = 6.0 V; max at -40 °C to +125 °C 4
input leakage current II -1 1 μA VI = VCC or GND; VCC = 6.0 V; at -40 °C to +125 °C 4
supply current ICC 160 μA VI = VCC or GND; IO = 0 A; VCC = 6.0 V; max at -40 °C to +125 °C 4
propagation delay CP to Qn tpd 55 250 ns CP to Qn; see Fig. 6; VCC = 2.0 V; CL = 50 pF; max at -40 °C to +125 °C 6
propagation delay CP to Qn tpd 20 50 ns CP to Qn; see Fig. 6; VCC = 4.5 V; CL = 50 pF; max at -40 °C to +125 °C 6
propagation delay CP to Qn tpd 16 43 ns CP to Qn; see Fig. 6; VCC = 6.0 V; CL = 50 pF; max at -40 °C to +125 °C 6
HIGH to LOW propagation delay MR to Qn tPHL 44 225 ns MR to Qn; see Fig. 7; VCC = 2.0 V; CL = 50 pF; max at -40 °C to +125 °C 6
HIGH to LOW propagation delay MR to Qn tPHL 16 45 ns MR to Qn; see Fig. 7; VCC = 4.5 V; CL = 50 pF; max at -40 °C to +125 °C 6
HIGH to LOW propagation delay MR to Qn tPHL 13 38 ns MR to Qn; see Fig. 7; VCC = 6.0 V; CL = 50 pF; max at -40 °C to +125 °C 6
transition time tt 19 110 ns Qn output; see Fig. 6; VCC = 2.0 V; CL = 50 pF; max at -40 °C to +125 °C 6
transition time tt 7 22 ns Qn output; see Fig. 6; VCC = 4.5 V; CL = 50 pF; max at -40 °C to +125 °C 6
transition time tt 6 19 ns Qn output; see Fig. 6; VCC = 6.0 V; CL = 50 pF; max at -40 °C to +125 °C 6
pulse width tW 120 17 ns CP input HIGH or LOW; see Fig. 6; VCC = 2.0 V; min at -40 °C to +125 °C 6
pulse width tW 24 6 ns CP input HIGH or LOW; see Fig. 6; VCC = 4.5 V; min at -40 °C to +125 °C 6
pulse width tW 20 5 ns CP input HIGH or LOW; see Fig. 6; VCC = 6.0 V; min at -40 °C to +125 °C 6
pulse width tW 120 12 ns MR input LOW; see Fig. 7; VCC = 2.0 V; min at -40 °C to +125 °C 6
pulse width tW 24 4 ns MR input LOW; see Fig. 7; VCC = 4.5 V; min at -40 °C to +125 °C 6
pulse width tW 20 3 ns MR input LOW; see Fig. 7; VCC = 6.0 V; min at -40 °C to +125 °C 6
recovery time trec 5 -11 ns MR to CP; see Fig. 7; VCC = 2.0 V; min at -40 °C to +125 °C 6
recovery time trec 5 -4 ns MR to CP; see Fig. 7; VCC = 4.5 V; min at -40 °C to +125 °C 6
recovery time trec 5 -3 ns MR to CP; see Fig. 7; VCC = 6.0 V; min at -40 °C to +125 °C 6
set-up time tsu 90 6 ns Dn to CP; see Fig. 6; VCC = 2.0 V; min at -40 °C to +125 °C 6
set-up time tsu 18 2 ns Dn to CP; see Fig. 6; VCC = 4.5 V; min at -40 °C to +125 °C 6
set-up time tsu 15 2 ns Dn to CP; see Fig. 6; VCC = 6.0 V; min at -40 °C to +125 °C 6
hold time th 3 -6 ns Dn to CP; see Fig. 6; VCC = 2.0 V; min at -40 °C to +125 °C 6
hold time th 3 -2 ns Dn to CP; see Fig. 6; VCC = 4.5 V; min at -40 °C to +125 °C 6
maximum frequency fmax 4 30 MHz CP input; see Fig. 6; VCC = 2.0 V; min at -40 °C to +125 °C 7
maximum frequency fmax 20 90 MHz CP input; see Fig. 6; VCC = 4.5 V; min at -40 °C to +125 °C 7
maximum frequency fmax 24 107 MHz CP input; see Fig. 6; VCC = 6.0 V; min at -40 °C to +125 °C 7

CAD (KiCad official)

  • Symbol: 74HC174PW
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: 74hc174pw-etched.step / 74hc174pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc174pw.step / 74hc174pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (14 pp, sha256 0dbc19171a4bbd3c, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF