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74HC174D

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Nexperia Flip Flops, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74HC174D

Nexperia · Flip Flops · SOIC-16

74HC174D from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MR input Asynchronous master reset input (active LOW); a LOW level resets all flip-flops and forces outputs Q0 to Q5 LOW.
2 Q0 output Flip-flop output 0, which takes the value loaded from D0 on the LOW-to-HIGH clock transition and is reset LOW by MR.
3 D0 input Data input 0; the level meeting set-up and hold time at the LOW-to-HIGH clock transition is stored in the flip-flop.
4 D1 input Data input 1; the level meeting set-up and hold time at the LOW-to-HIGH clock transition is stored in the flip-flop.
5 Q1 output Flip-flop output 1, which takes the value loaded from D1 on the LOW-to-HIGH clock transition and is reset LOW by MR.
6 D2 input Data input 2; the level meeting set-up and hold time at the LOW-to-HIGH clock transition is stored in the flip-flop.
7 Q2 output Flip-flop output 2, which takes the value loaded from D2 on the LOW-to-HIGH clock transition and is reset LOW by MR.
8 GND power_in Ground (0 V) reference for all voltages.
9 CP input Clock input, LOW-to-HIGH edge-triggered; the stored data is loaded into all six flip-flops on this edge.
10 Q3 output Flip-flop output 3, which takes the value loaded from D3 on the LOW-to-HIGH clock transition and is reset LOW by MR.
11 D3 input Data input 3; the level meeting set-up and hold time at the LOW-to-HIGH clock transition is stored in the flip-flop.
12 Q4 output Flip-flop output 4, which takes the value loaded from D4 on the LOW-to-HIGH clock transition and is reset LOW by MR.
13 D4 input Data input 4; the level meeting set-up and hold time at the LOW-to-HIGH clock transition is stored in the flip-flop.
14 D5 input Data input 5; the level meeting set-up and hold time at the LOW-to-HIGH clock transition is stored in the flip-flop.
15 Q5 output Flip-flop output 5, which takes the value loaded from D5 on the LOW-to-HIGH clock transition and is reset LOW by MR.
16 VCC power_in Positive supply voltage; 2.0 V to 6.0 V for 74HC174 and 4.5 V to 5.5 V for 74HCT174 per recommended operating conditions.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOIC-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC supply voltage VCC 2 5 6 V 74HC174 column 4
Input voltage VI 0 V 74HC174 column; printed max is VCC (symbolic, not numeric) 4
Output voltage VO 0 V 74HC174 column; printed max is VCC (symbolic, not numeric) 4
Ambient temperature Tamb -40 125 °C 4
Input transition rise and fall rate Δt/ΔV 625 ns/V VCC = 2.0 V 4
Input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 4
Input transition rise and fall rate Δt/ΔV 83 ns/V VCC = 6.0 V 4
Supply voltage VCC -0.5 7 V 3
Input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 3
Output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 3
Output current IO -25 25 mA -0.5 V < VO < VCC + 0.5 V 3
Supply current ICC 50 mA 3
Ground current IGND -50 mA 3
Storage temperature Tstg -65 150 °C 3
Total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 3
HIGH-level input voltage VIH 1.5 1.2 V VCC = 2.0 V; -40 °C to +125 °C min 4
HIGH-level input voltage VIH 3.15 2.4 V VCC = 4.5 V; -40 °C to +125 °C min 4
HIGH-level input voltage VIH 4.2 3.2 V VCC = 6.0 V; -40 °C to +125 °C min 4
LOW-level input voltage VIL 0.8 0.5 V VCC = 2.0 V; -40 °C to +125 °C max 4
LOW-level input voltage VIL 2.1 1.35 V VCC = 4.5 V; -40 °C to +125 °C max 4
LOW-level input voltage VIL 2.8 1.8 V VCC = 6.0 V; -40 °C to +125 °C max 4
HIGH-level output voltage VOH 1.9 2 V IO = -20 μA; VCC = 2.0 V; -40 °C to +125 °C min 4
HIGH-level output voltage VOH 4.4 4.5 V IO = -20 μA; VCC = 4.5 V; -40 °C to +125 °C min 4
HIGH-level output voltage VOH 5.9 6 V IO = -20 μA; VCC = 6.0 V; -40 °C to +125 °C min 4
HIGH-level output voltage VOH 3.7 4.32 V IO = -4.0 mA; VCC = 4.5 V; -40 °C to +125 °C min 4
HIGH-level output voltage VOH 5.2 5.81 V IO = -5.2 mA; VCC = 6.0 V; -40 °C to +125 °C min 4
LOW-level output voltage VOL 0 0.1 V IO = 20 μA; VCC = 2.0 V; -40 °C to +125 °C max 4
LOW-level output voltage VOL 0.15 0.4 V IO = 4.0 mA; VCC = 4.5 V; -40 °C to +125 °C max 4
LOW-level output voltage VOL 0.16 0.4 V IO = 5.2 mA; VCC = 6.0 V; -40 °C to +125 °C max 4
Input leakage current II -1 1 μA VI = VCC or GND; VCC = 6.0 V; -40 °C to +125 °C 4
Supply current ICC 160 μA VI = VCC or GND; IO = 0 A; VCC = 6.0 V; -40 °C to +125 °C 4
CP to Qn propagation delay (tpd) tpd 55 250 ns VCC = 2.0 V; CL = 50 pF; -40 °C to +125 °C; see Fig. 6 6
CP to Qn propagation delay (tpd) tpd 20 50 ns VCC = 4.5 V; CL = 50 pF; -40 °C to +125 °C; see Fig. 6 6
CP to Qn propagation delay (tpd) tpd 16 43 ns VCC = 6.0 V; CL = 50 pF; -40 °C to +125 °C; see Fig. 6 6
MR to Qn HIGH to LOW propagation delay (tPHL) tPHL 44 225 ns VCC = 2.0 V; CL = 50 pF; -40 °C to +125 °C; see Fig. 7 6
MR to Qn HIGH to LOW propagation delay (tPHL) tPHL 16 45 ns VCC = 4.5 V; CL = 50 pF; -40 °C to +125 °C; see Fig. 7 6
MR to Qn HIGH to LOW propagation delay (tPHL) tPHL 13 38 ns VCC = 6.0 V; CL = 50 pF; -40 °C to +125 °C; see Fig. 7 6
Qn output transition time (tt) tt 19 110 ns VCC = 2.0 V; CL = 50 pF; -40 °C to +125 °C; see Fig. 6 6
Qn output transition time (tt) tt 7 22 ns VCC = 4.5 V; CL = 50 pF; -40 °C to +125 °C; see Fig. 6 6
Qn output transition time (tt) tt 6 19 ns VCC = 6.0 V; CL = 50 pF; -40 °C to +125 °C; see Fig. 6 6
CP input pulse width HIGH or LOW (tW) tW 120 17 ns VCC = 2.0 V; -40 °C to +125 °C; see Fig. 6 6
CP input pulse width HIGH or LOW (tW) tW 24 6 ns VCC = 4.5 V; -40 °C to +125 °C; see Fig. 6 6
CP input pulse width HIGH or LOW (tW) tW 20 5 ns VCC = 6.0 V; -40 °C to +125 °C; see Fig. 6 6
MR input LOW pulse width (tW) tW 120 12 ns VCC = 2.0 V; -40 °C to +125 °C; see Fig. 7 6
MR input LOW pulse width (tW) tW 24 4 ns VCC = 4.5 V; -40 °C to +125 °C; see Fig. 7 6
MR input LOW pulse width (tW) tW 20 3 ns VCC = 6.0 V; -40 °C to +125 °C; see Fig. 7 6
Recovery time MR to CP (trec) trec 5 -11 ns VCC = 2.0 V; -40 °C to +125 °C; see Fig. 7 6
Recovery time MR to CP (trec) trec 5 -4 ns VCC = 4.5 V; -40 °C to +125 °C; see Fig. 7 6
Recovery time MR to CP (trec) trec 5 -3 ns VCC = 6.0 V; -40 °C to +125 °C; see Fig. 7 6
Set-up time Dn to CP (tsu) tsu 90 6 ns VCC = 2.0 V; -40 °C to +125 °C; see Fig. 6 6
Set-up time Dn to CP (tsu) tsu 18 2 ns VCC = 4.5 V; -40 °C to +125 °C; see Fig. 6 6
Set-up time Dn to CP (tsu) tsu 15 2 ns VCC = 6.0 V; -40 °C to +125 °C; see Fig. 6 6
Hold time Dn to CP (th) th 3 -6 ns VCC = 2.0 V; -40 °C to +125 °C; see Fig. 6 6
Hold time Dn to CP (th) th 3 -2 ns VCC = 4.5 V; -40 °C to +125 °C; see Fig. 6 6
Maximum clock frequency (fmax) fmax 4 30 MHz VCC = 2.0 V; -40 °C to +125 °C; see Fig. 6 7
Maximum clock frequency (fmax) fmax 20 90 MHz VCC = 4.5 V; -40 °C to +125 °C; see Fig. 6 7
Maximum clock frequency (fmax) fmax 24 107 MHz VCC = 6.0 V; -40 °C to +125 °C; see Fig. 6 7

CAD (KiCad official)

  • Symbol: 74HC174D
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: 74hc174d-etched.step / 74hc174d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc174d.step / 74hc174d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (14 pp, sha256 0dbc19171a4bbd3c, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF