component
74HC166D
Public Made by Adomby adom
Nexperia Shifting Register, SOIC-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+174−8@@ -1,13 +1,184 @@ {+ "schema_version": 1,+ "type": "component", "slug": "74hc166d",+ "title": "74HC166D",+ "brief": "Nexperia Shifting Register, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "Nexperia Shifting Register, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "logic", "74hc166d" ],+ "component": {+ "mpn": "74HC166D",+ "manufacturer": "Nexperia",+ "package": "SOIC-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Shifting Register",+ "datasheet": "https://assets.nexperia.com/documents/data-sheet/74HC166D.pdf",+ "parts": {+ "symbol": "74hc166d.kicad_sym",+ "footprint": "74hc166d.kicad_mod",+ "model_3d": "74hc166d.glb",+ "model_3d_step": "74hc166d.step",+ "lbr": "74hc166d.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "DS",+ "type": "input",+ "description": "Serial data input. Data present at DS is loaded into the first flip-flop on each LOW-to-HIGH transition of CP when PE is HIGH (serial shift mode)."+ },+ {+ "number": "2",+ "name": "D0",+ "type": "input",+ "description": "Parallel data input bit 0. Latched into stage 1 of the shift register on the next LOW-to-HIGH clock edge when PE is LOW."+ },+ {+ "number": "3",+ "name": "D1",+ "type": "input",+ "description": "Parallel data input bit 1. Loaded into the shift register on the next LOW-to-HIGH clock edge while PE is LOW."+ },+ {+ "number": "4",+ "name": "D2",+ "type": "input",+ "description": "Parallel data input bit 2. Loaded into the shift register on the next LOW-to-HIGH clock edge while PE is LOW."+ },+ {+ "number": "5",+ "name": "D3",+ "type": "input",+ "description": "Parallel data input bit 3. Loaded into the shift register on the next LOW-to-HIGH clock edge while PE is LOW."+ },+ {+ "number": "6",+ "name": "CE",+ "type": "input",+ "description": "Clock enable input, active LOW. A LOW allows the clock signal to reach the internal flip-flops; a HIGH on CE disables the CP input and the register holds its state."+ },+ {+ "number": "7",+ "name": "CP",+ "type": "input",+ "description": "Clock input, LOW-to-HIGH edge-triggered. Rising edges load parallel data (if PE=LOW) or shift serial data (if PE=HIGH) through the 8-bit register."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference, 0 V. Common return for supply and I/O."+ },+ {+ "number": "9",+ "name": "MR",+ "type": "input",+ "description": "Asynchronous master reset input, active LOW. A LOW immediately clears all eight flip-flops independently of the clock."+ },+ {+ "number": "10",+ "name": "D4",+ "type": "input",+ "description": "Parallel data input bit 4. Loaded into the shift register on the next LOW-to-HIGH clock edge while PE is LOW."+ },+ {+ "number": "11",+ "name": "D5",+ "type": "input",+ "description": "Parallel data input bit 5. Loaded into the shift register on the next LOW-to-HIGH clock edge while PE is LOW."+ },+ {+ "number": "12",+ "name": "D6",+ "type": "input",+ "description": "Parallel data input bit 6. Loaded into the shift register on the next LOW-to-HIGH clock edge while PE is LOW."+ },+ {+ "number": "13",+ "name": "Q7",+ "type": "output",+ "description": "Serial data output from the last (8th) stage of the shift register. Drives shifted-out data for cascading or serial capture."+ },+ {+ "number": "14",+ "name": "D7",+ "type": "input",+ "description": "Parallel data input bit 7. Loaded into the last stage of the shift register on the next LOW-to-HIGH clock edge while PE is LOW."+ },+ {+ "number": "15",+ "name": "PE",+ "type": "input",+ "description": "Parallel enable input, active LOW. LOW loads D0-D7 into the register on the next clock rising edge; HIGH selects serial shift mode with DS as the input."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage. Operating range 2.0 V to 6.0 V for 74HC166 (4.5 V to 5.5 V for 74HCT166). Decouple to GND close to the pin."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://assets.nexperia.com/documents/data-sheet/74HC166D.pdf",+ "pages": 17,+ "sha256": "eaa7369d88204bc2",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "Nexperia",+ "Package": "SOIC-16",+ "Category": "Logic",+ "Pins": "16"+ }+ },+ "variants": [+ {+ "mpn": "74HC166DD",+ "kind": "packaging"+ },+ {+ "mpn": "74HC166DPW",+ "kind": "packaging"+ }+ ],+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "74hc166d"+ ],+ "discovery_pitch": "74HC166D (Nexperia) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +196,5 @@ "docs/74hc166d-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }