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74HC166D

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by adom

Nexperia Shifting Register, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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74HC166D

Nexperia · Shifting Register · SOIC-16

74HC166D from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DS input Serial data input. Data present at DS is loaded into the first flip-flop on each LOW-to-HIGH transition of CP when PE is HIGH (serial shift mode).
2 D0 input Parallel data input bit 0. Latched into stage 1 of the shift register on the next LOW-to-HIGH clock edge when PE is LOW.
3 D1 input Parallel data input bit 1. Loaded into the shift register on the next LOW-to-HIGH clock edge while PE is LOW.
4 D2 input Parallel data input bit 2. Loaded into the shift register on the next LOW-to-HIGH clock edge while PE is LOW.
5 D3 input Parallel data input bit 3. Loaded into the shift register on the next LOW-to-HIGH clock edge while PE is LOW.
6 CE input Clock enable input, active LOW. A LOW allows the clock signal to reach the internal flip-flops; a HIGH on CE disables the CP input and the register holds its state.
7 CP input Clock input, LOW-to-HIGH edge-triggered. Rising edges load parallel data (if PE=LOW) or shift serial data (if PE=HIGH) through the 8-bit register.
8 GND power_in Ground reference, 0 V. Common return for supply and I/O.
9 MR input Asynchronous master reset input, active LOW. A LOW immediately clears all eight flip-flops independently of the clock.
10 D4 input Parallel data input bit 4. Loaded into the shift register on the next LOW-to-HIGH clock edge while PE is LOW.
11 D5 input Parallel data input bit 5. Loaded into the shift register on the next LOW-to-HIGH clock edge while PE is LOW.
12 D6 input Parallel data input bit 6. Loaded into the shift register on the next LOW-to-HIGH clock edge while PE is LOW.
13 Q7 output Serial data output from the last (8th) stage of the shift register. Drives shifted-out data for cascading or serial capture.
14 D7 input Parallel data input bit 7. Loaded into the last stage of the shift register on the next LOW-to-HIGH clock edge while PE is LOW.
15 PE input Parallel enable input, active LOW. LOW loads D0-D7 into the register on the next clock rising edge; HIGH selects serial shift mode with DS as the input.
16 VCC power_in Positive supply voltage. Operating range 2.0 V to 6.0 V for 74HC166 (4.5 V to 5.5 V for 74HCT166). Decouple to GND close to the pin.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOIC-16
Category Logic
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • 74HC166DD
  • 74HC166DPW

CAD (KiCad official)

  • Symbol: 74HC166D
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: 74hc166d-etched.step / 74hc166d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc166d.step / 74hc166d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (17 pp, sha256 eaa7369d88204bc2, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF