74HC165PW

{
  "schema_version": 1,
  "type": "component",
  "slug": "74hc165pw",
  "title": "74HC165PW",
  "brief": "Nexperia Shifting Register, TSSOP-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.2.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "74hc165pw"
  ],
  "component": {
    "mpn": "74HC165PW",
    "manufacturer": "Nexperia",
    "package": "TSSOP-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Shifting Register",
    "datasheet": "https://assets.nexperia.com/documents/data-sheet/74HC165PW.pdf",
    "parts": {
      "symbol": "74hc165pw.kicad_sym",
      "footprint": "74hc165pw.kicad_mod",
      "model_3d": "74hc165pw-etched.glb",
      "model_3d_plain": "74hc165pw.glb",
      "model_3d_step": "74hc165pw-etched.step",
      "model_3d_step_plain": "74hc165pw.step",
      "lbr": "74hc165pw.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "PL",
        "type": "input",
        "description": "Asynchronous parallel load input (active LOW). When PL is LOW, data from D0-D7 is loaded into the shift register asynchronously; when HIGH, data enters serially at DS on rising CP edges."
      },
      {
        "number": "2",
        "name": "CP",
        "type": "input",
        "description": "Clock input, LOW-to-HIGH edge-triggered. Serial data is shifted on rising edges when CE is LOW and PL is HIGH. Max fmax typically 51 MHz at VCC=4.5 V."
      },
      {
        "number": "3",
        "name": "D4",
        "type": "input",
        "description": "Parallel data input bit 4. Loaded into internal shift register stage Q4 when PL is asserted LOW."
      },
      {
        "number": "4",
        "name": "D5",
        "type": "input",
        "description": "Parallel data input bit 5. Loaded into internal shift register stage Q5 when PL is asserted LOW."
      },
      {
        "number": "5",
        "name": "D6",
        "type": "input",
        "description": "Parallel data input bit 6. Loaded into internal shift register stage Q6 when PL is asserted LOW."
      },
      {
        "number": "6",
        "name": "D7",
        "type": "input",
        "description": "Parallel data input bit 7 (last stage). Loaded into internal shift register stage Q7 when PL is asserted LOW and appears at Q7 output."
      },
      {
        "number": "7",
        "name": "Q7",
        "type": "output",
        "description": "Complementary (inverted) serial output from the last shift-register stage. Provides logical complement of Q7."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference (0 V)."
      },
      {
        "number": "9",
        "name": "Q7",
        "type": "output",
        "description": "Serial output from the last stage of the shift register. Cascade this pin to DS of a downstream 74HC165 for wider registers."
      },
      {
        "number": "10",
        "name": "DS",
        "type": "input",
        "description": "Serial data input. Sampled on the LOW-to-HIGH CP edge when CE is LOW and PL is HIGH; drives the first register stage."
      },
      {
        "number": "11",
        "name": "D0",
        "type": "input",
        "description": "Parallel data input bit 0. Loaded into internal shift register stage Q0 when PL is asserted LOW."
      },
      {
        "number": "12",
        "name": "D1",
        "type": "input",
        "description": "Parallel data input bit 1. Loaded into internal shift register stage Q1 when PL is asserted LOW."
      },
      {
        "number": "13",
        "name": "D2",
        "type": "input",
        "description": "Parallel data input bit 2. Loaded into internal shift register stage Q2 when PL is asserted LOW."
      },
      {
        "number": "14",
        "name": "D3",
        "type": "input",
        "description": "Parallel data input bit 3. Loaded into internal shift register stage Q3 when PL is asserted LOW."
      },
      {
        "number": "15",
        "name": "CE",
        "type": "input",
        "description": "Clock enable input (active LOW). When CE is LOW, data is shifted on CP rising edges; when HIGH, CP is disabled and the register holds its state."
      },
      {
        "number": "16",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply voltage. 2.0 V to 6.0 V for 74HC165; 4.5 V to 5.5 V for 74HCT165."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://assets.nexperia.com/documents/data-sheet/74HC165PW.pdf",
        "pages": 18,
        "sha256": "376fad78107f38d0",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "pin1": {
      "pad": "1",
      "at": [
        -2.8625,
        -2.275
      ],
      "corner": "top-left",
      "source": "silk-marker",
      "derived_from": "TSSOP-16_4.4x5mm_P0.65mm@sha256:fbac79fc5f310754",
      "mark": "drawn"
    },
    "logic": {
      "family_id": "74HC165",
      "logic_family": "74HC",
      "function_code": "165",
      "function_class": "ShiftRegister",
      "function_name": "8-Bit PISO Shift Register",
      "manufacturer": null,
      "is_specialty": false
    },
    "models_3d": [
      {
        "file": "74hc165pw.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.4,
          5.0,
          1.1
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "6ad5e98224d02a427d9a6b929a28dbc158b9925fba5adec12db05079f1016948",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "74hc165pw-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.4,
          5.0,
          1.1
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "f5894adf5c1a72e047d4434589a8c8f1f4e32cf52b92bc0069420fcacdd860fc",
        "checked": "2026-10-19",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Nexperia",
      "Package": "TSSOP-16",
      "Category": "Logic",
      "Pins": "16"
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "74hc165pw"
  ],
  "discovery_pitch": "74HC165PW (Nexperia) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "74hc165pw.kicad_sym",
    "74hc165pw.kicad_mod",
    "74hc165pw.glb",
    "74hc165pw.step",
    "74hc165pw-etched.step",
    "74hc165pw.lbr",
    "docs/hero.png",
    "docs/74hc165pw-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
    "public": true
  },
  "updated_at": "2026-09-24T14:54:59.654Z"
}