74HC165M

{
  "schema_version": 1,
  "type": "component",
  "slug": "74hc165m",
  "title": "74HC165M",
  "brief": "HGSEMI Shifting Register, SOP-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.2.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "74hc165m"
  ],
  "component": {
    "mpn": "74HC165M",
    "manufacturer": "HGSEMI",
    "package": "SOP-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Shifting Register",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/900544ca85132853f1e881713b73de8c.pdf",
    "parts": {
      "symbol": "74hc165m.kicad_sym",
      "footprint": "74hc165m.kicad_mod",
      "model_3d": "74hc165m-etched.glb",
      "model_3d_plain": "74hc165m.glb",
      "model_3d_step": "74hc165m-etched.step",
      "model_3d_step_plain": "74hc165m.step",
      "lbr": "74hc165m.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "PL",
        "type": "input",
        "description": "Asynchronous parallel load input, active low. When PL is low, the state of D0-D7 is loaded into the internal register regardless of CP or CE."
      },
      {
        "number": "2",
        "name": "CP",
        "type": "input",
        "description": "Clock input. Data is shifted on the low-to-high (rising) edge of CP when CE is low and PL is high."
      },
      {
        "number": "3",
        "name": "D4",
        "type": "input",
        "description": "Parallel data input bit 4. Loaded into the internal shift register when PL is asserted low."
      },
      {
        "number": "4",
        "name": "D5",
        "type": "input",
        "description": "Parallel data input bit 5. Loaded into the internal shift register when PL is asserted low."
      },
      {
        "number": "5",
        "name": "D6",
        "type": "input",
        "description": "Parallel data input bit 6. Loaded into the internal shift register when PL is asserted low."
      },
      {
        "number": "6",
        "name": "D7",
        "type": "input",
        "description": "Parallel data input bit 7 (last stage). Loaded into the internal shift register when PL is asserted low."
      },
      {
        "number": "7",
        "name": "/Q7",
        "type": "output",
        "description": "Complementary (inverted) serial output of the last stage of the shift register."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference (0 V)."
      },
      {
        "number": "9",
        "name": "Q7",
        "type": "output",
        "description": "True serial output of the last stage of the shift register."
      },
      {
        "number": "10",
        "name": "DS",
        "type": "input",
        "description": "Serial data input. Sampled into the first stage of the shift register on the rising edge of CP when CE is low."
      },
      {
        "number": "11",
        "name": "D0",
        "type": "input",
        "description": "Parallel data input bit 0. Loaded into the internal shift register when PL is asserted low."
      },
      {
        "number": "12",
        "name": "D1",
        "type": "input",
        "description": "Parallel data input bit 1. Loaded into the internal shift register when PL is asserted low."
      },
      {
        "number": "13",
        "name": "D2",
        "type": "input",
        "description": "Parallel data input bit 2. Loaded into the internal shift register when PL is asserted low."
      },
      {
        "number": "14",
        "name": "D3",
        "type": "input",
        "description": "Parallel data input bit 3. Loaded into the internal shift register when PL is asserted low."
      },
      {
        "number": "15",
        "name": "CE",
        "type": "input",
        "description": "Clock enable input, active low. When CE is high the CP input is inhibited; when CE is low the clock is enabled."
      },
      {
        "number": "16",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply voltage. Recommended operating range 2.0 V to 6.0 V (typ. 5.0 V); absolute maximum 7 V."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/900544ca85132853f1e881713b73de8c.pdf",
        "pages": 17,
        "sha256": "41529863b9a0876e",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "pin1": {
      "pad": "1",
      "at": [
        -2.475,
        -4.445
      ],
      "corner": "top-left",
      "source": "silk-marker",
      "derived_from": "SOIC-16_3.9x9.9mm_P1.27mm@sha256:f9b5075740f7816c",
      "mark": "drawn"
    },
    "logic": {
      "family_id": "74HC165",
      "logic_family": "74HC",
      "function_code": "165",
      "function_class": "ShiftRegister",
      "function_name": "8-Bit PISO Shift Register",
      "manufacturer": null,
      "is_specialty": false
    },
    "models_3d": [
      {
        "file": "74hc165m.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          9.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "74hc165m-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          9.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "7d6149b593f4cb3f307e4a118c43f7ef3c193f5a3dc7bb75a21cc370d95b3891",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "HGSEMI",
      "Package": "SOP-16",
      "Category": "Logic",
      "Pins": "16"
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "74hc165m"
  ],
  "discovery_pitch": "74HC165M (HGSEMI) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "74hc165m.kicad_sym",
    "74hc165m.kicad_mod",
    "74hc165m.glb",
    "74hc165m.step",
    "74hc165m-etched.step",
    "74hc165m.lbr",
    "docs/hero.png",
    "docs/74hc165m-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
    "public": true
  },
  "updated_at": "2026-09-24T14:54:50.029Z"
}