component
74HC165M-JSM
Public Made by Adomby adom
JSMSEMI Shift Registers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
74HC165M-JSM
JSMSEMI · Shift Registers · SOP-16
74HC165M-JSM from JSMSEMI, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SH/LD | input | Shift/load input: a low level enables the parallel data inputs A-H independently of CLK, CLK INH and SER, and a high level inhibits parallel loading. |
| 2 | CLK | input | Clock input: a low-to-high transition shifts data toward QH while SH/LD is high and CLK INH is low, and its function is interchangeable with CLK INH. |
| 3 | E | input | Parallel data input E, enabled by a low level at SH/LD. |
| 4 | F | input | Parallel data input F, enabled by a low level at SH/LD. |
| 5 | G | input | Parallel data input G, enabled by a low level at SH/LD. |
| 6 | H | input | Parallel data input H, enabled by a low level at SH/LD. |
| 7 | QH̅ | output | Complementary serial output, the inverse of QH. |
| 8 | GND | power_in | Ground. |
| 9 | QH | output | Serial output of the last register stage, which receives the data shifted toward it. |
| 10 | SER | input | Serial data input, shifted into the first register stage on each clock. |
| 11 | A | input | Parallel data input A, enabled by a low level at SH/LD. |
| 12 | B | input | Parallel data input B, enabled by a low level at SH/LD. |
| 13 | C | input | Parallel data input C, enabled by a low level at SH/LD. |
| 14 | D | input | Parallel data input D, enabled by a low level at SH/LD. |
| 15 | CLK INH | input | Clock inhibit input: a high level inhibits clocking, and a low-to-high transition while CLK is low also clocks the device. |
| 16 | VCC | power_in | Positive supply voltage, with a wide operating range of 2 V to 6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | JSMSEMI |
| Package | SOP-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
74HC165M-JSM - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files:
74hc165m-jsm-etched.step/74hc165m-jsm-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc165m-jsm.step/74hc165m-jsm.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: JSMSEMI datasheet (9 pp, sha256
b37c33db7606e1ed, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 74HC165M-JSM
**JSMSEMI** · Shift Registers · SOP-16
74HC165M-JSM from JSMSEMI, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SH/LD | input | Shift/load input: a low level enables the parallel data inputs A-H independently of CLK, CLK INH and SER, and a high level inhibits parallel loading. |
| 2 | CLK | input | Clock input: a low-to-high transition shifts data toward QH while SH/LD is high and CLK INH is low, and its function is interchangeable with CLK INH. |
| 3 | E | input | Parallel data input E, enabled by a low level at SH/LD. |
| 4 | F | input | Parallel data input F, enabled by a low level at SH/LD. |
| 5 | G | input | Parallel data input G, enabled by a low level at SH/LD. |
| 6 | H | input | Parallel data input H, enabled by a low level at SH/LD. |
| 7 | QH̅ | output | Complementary serial output, the inverse of QH. |
| 8 | GND | power_in | Ground. |
| 9 | QH | output | Serial output of the last register stage, which receives the data shifted toward it. |
| 10 | SER | input | Serial data input, shifted into the first register stage on each clock. |
| 11 | A | input | Parallel data input A, enabled by a low level at SH/LD. |
| 12 | B | input | Parallel data input B, enabled by a low level at SH/LD. |
| 13 | C | input | Parallel data input C, enabled by a low level at SH/LD. |
| 14 | D | input | Parallel data input D, enabled by a low level at SH/LD. |
| 15 | CLK INH | input | Clock inhibit input: a high level inhibits clocking, and a low-to-high transition while CLK is low also clocks the device. |
| 16 | VCC | power_in | Positive supply voltage, with a wide operating range of 2 V to 6 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | JSMSEMI |
| Package | SOP-16 |
| Category | Logic |
| Pins | 16 |
## CAD (KiCad official)
- Symbol: `74HC165M-JSM`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files: `74hc165m-jsm-etched.step` / `74hc165m-jsm-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74hc165m-jsm.step` / `74hc165m-jsm.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [JSMSEMI datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603352392914526208) (9 pp, sha256 `b37c33db7606e1ed`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/74hc165m-jsm-datasheet.pdf)