74HC165D

@@ -0,0 +1,57 @@+# 74HC165D++**Nexperia** · Shifting Register · SOIC-16++74HC165D from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | /PL | input | Asynchronous parallel load input, active LOW. When LOW, data on D0-D7 is loaded into the shift register asynchronously. |+| 2 | CP | input | Clock input, LOW-to-HIGH edge-triggered. Data is shifted on the rising edge when /CE is LOW. |+| 3 | D4 | input | Parallel data input bit 4 (loaded into the shift register when /PL is LOW). |+| 4 | D5 | input | Parallel data input bit 5 (loaded into the shift register when /PL is LOW). |+| 5 | D6 | input | Parallel data input bit 6 (loaded into the shift register when /PL is LOW). |+| 6 | D7 | input | Parallel data input bit 7, the last (MSB-side) stage (loaded into the shift register when /PL is LOW). |+| 7 | /Q7 | output | Complementary (inverted) serial output from the last shift-register stage. |+| 8 | GND | power_in | Ground reference (0 V). |+| 9 | Q7 | output | Serial (non-inverted) output from the last shift-register stage. |+| 10 | DS | input | Serial data input. Data present here is shifted into the first stage on the LOW-to-HIGH clock transition (when /CE is LOW and /PL is HIGH). |+| 11 | D0 | input | Parallel data input bit 0 (loaded into the shift register when /PL is LOW). |+| 12 | D1 | input | Parallel data input bit 1 (loaded into the shift register when /PL is LOW). |+| 13 | D2 | input | Parallel data input bit 2 (loaded into the shift register when /PL is LOW). |+| 14 | D3 | input | Parallel data input bit 3 (loaded into the shift register when /PL is LOW). |+| 15 | /CE | input | Clock enable input, active LOW. When LOW, data is shifted on the rising edge of CP; a HIGH on /CE disables the CP input (hold). |+| 16 | VCC | power_in | Positive supply voltage. Recommended range 2.0 V to 6.0 V for 74HC165 (4.5-5.5 V for 74HCT165); absolute max 7 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Nexperia |+| Package | SOIC-16 |+| Category | Logic |+| Pins | 16 |++## Ordering variants++- `74HC165DD`+- `74HC165DPW`+- `74HC165DBQ`++## CAD (KiCad official)++- Symbol: `74HC165D`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/74HC165D.pdf) (18 pp, sha256 `376fad78107f38d0`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/74hc165d-datasheet.pdf)

@@ -0,0 +1,34 @@+{+  "slug": "74hc165d",+  "version": "0.1.0",+  "type": "component",+  "description": "Nexperia Shifting Register, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "logic",+    "74hc165d"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "74hc165d.kicad_sym",+    "74hc165d.kicad_mod",+    "74hc165d.glb",+    "74hc165d.step",+    "74hc165d.lbr",+    "docs/hero.png",+    "docs/74hc165d-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file