component
74HC165D
Public Made by Adomby adom
Nexperia Shifting Register, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.
← Commit history
74hc165d 0.1.1: component block filled (mpn, maker, package, datasheet, pins, symbol/footprint/lbr declared, license, LCSC); CAD unchanged (Ray review #937)
1 file changed
+154−14
page.json+154−14@@ -24,9 +24,15 @@ "docs/hero.png", "docs/74hc165d-datasheet.pdf", "viewers/symbol.html",- "viewers/footprint.html"+ "viewers/footprint.html",+ "74hc165d-etched.step",+ "74hc165d-hero.glb",+ "74hc165d-hero.overlay.json",+ "74hc165d-etched.glb" ],- "visibility": "public",+ "visibility": {+ "public": true+ }, "author": { "name": "Ray", "email": "[email protected]"@@ -44,8 +50,11 @@ "parts": { "model_3d_step": "74hc165d-etched.step", "model_3d_step_plain": "74hc165d.step",- "model_3d": "74hc165d-etched.glb",- "model_3d_plain": "74hc165d.glb"+ "model_3d": "74hc165d-hero.glb",+ "model_3d_plain": "74hc165d-etched.glb",+ "symbol": "74hc165d.kicad_sym",+ "footprint": "74hc165d.kicad_mod",+ "lbr": "74hc165d.lbr" }, "models_3d": [ {@@ -56,12 +65,12 @@ "origin": "footprint origin = pad-pattern centre", "seat": "z = 0", "extents_mm": [- 6,+ 6.0, 9.9, 1.75 ],- "zmin_mm": 0,- "centre_offset_mm": 0,+ "zmin_mm": -0.0,+ "centre_offset_mm": 0.0, "footprint_binding": "identity", "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf", "checked": "2026-10-07",@@ -75,20 +84,151 @@ "origin": "footprint origin = pad-pattern centre", "seat": "z = 0", "extents_mm": [- 6,+ 6.0, 9.9, 1.75 ],- "zmin_mm": 0,- "centre_offset_mm": 0,+ "zmin_mm": -0.0,+ "centre_offset_mm": 0.0, "footprint_binding": "identity", "sha256": "81f1051bd1683dd6fd6a2e8f21b416b9e6f11659778a54697cc2f97ffb68a855", "checked": "2026-10-07", "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)" }- ]+ ],+ "mpn": "74HC165D",+ "manufacturer": "Nexperia",+ "package": "SOIC-16",+ "pin_count": 16,+ "category": "Logic ICs",+ "subcategory": "Shifting Register",+ "datasheet": "https://assets.nexperia.com/documents/data-sheet/74HC_HCT165.pdf",+ "pins": [+ {+ "number": "1",+ "name": "/PL",+ "type": "input",+ "description": "Asynchronous parallel load input, active LOW. When LOW, data on D0-D7 is loaded into the shift register asynchronously."+ },+ {+ "number": "2",+ "name": "CP",+ "type": "input",+ "description": "Clock input, LOW-to-HIGH edge-triggered. Data is shifted on the rising edge when /CE is LOW."+ },+ {+ "number": "3",+ "name": "D4",+ "type": "input",+ "description": "Parallel data input bit 4 (loaded into the shift register when /PL is LOW)."+ },+ {+ "number": "4",+ "name": "D5",+ "type": "input",+ "description": "Parallel data input bit 5 (loaded into the shift register when /PL is LOW)."+ },+ {+ "number": "5",+ "name": "D6",+ "type": "input",+ "description": "Parallel data input bit 6 (loaded into the shift register when /PL is LOW)."+ },+ {+ "number": "6",+ "name": "D7",+ "type": "input",+ "description": "Parallel data input bit 7, the last (MSB-side) stage (loaded into the shift register when /PL is LOW)."+ },+ {+ "number": "7",+ "name": "/Q7",+ "type": "output",+ "description": "Complementary (inverted) serial output from the last shift-register stage."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference (0 V)."+ },+ {+ "number": "9",+ "name": "Q7",+ "type": "output",+ "description": "Serial (non-inverted) output from the last shift-register stage."+ },+ {+ "number": "10",+ "name": "DS",+ "type": "input",+ "description": "Serial data input. Data present here is shifted into the first stage on the LOW-to-HIGH clock transition (when /CE is LOW and /PL is HIGH)."+ },+ {+ "number": "11",+ "name": "D0",+ "type": "input",+ "description": "Parallel data input bit 0 (loaded into the shift register when /PL is LOW)."+ },+ {+ "number": "12",+ "name": "D1",+ "type": "input",+ "description": "Parallel data input bit 1 (loaded into the shift register when /PL is LOW)."+ },+ {+ "number": "13",+ "name": "D2",+ "type": "input",+ "description": "Parallel data input bit 2 (loaded into the shift register when /PL is LOW)."+ },+ {+ "number": "14",+ "name": "D3",+ "type": "input",+ "description": "Parallel data input bit 3 (loaded into the shift register when /PL is LOW)."+ },+ {+ "number": "15",+ "name": "/CE",+ "type": "input",+ "description": "Clock enable input, active LOW. When LOW, data is shifted on the rising edge of CP; a HIGH on /CE disables the CP input (hold)."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage. Recommended range 2.0 V to 6.0 V for 74HC165 (4.5-5.5 V for 74HCT165); absolute max 7 V."+ }+ ],+ "distributor_links": {+ "lcsc": "C5613"+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "aliases": [+ "74HC165D,653"+ ],+ "provenance": {+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "cad_footprint": "KiCad SOIC-16_3.9x9.9mm_P1.27mm",+ "pins": {+ "total": 16,+ "source": "README pin table from the 2026-08-24 datasheet extraction (ds2sf); equals the KiCad symbol and the footprint pads"+ },+ "component_block": {+ "at": "2026-11-09",+ "by": "part-reviewer (Ray review #937)",+ "what": "component block filled from the page's own README, symbol and footprint plus Component Ocean (LCSC, datasheet URL); CAD unchanged"+ },+ "datasheet": {+ "url": "https://assets.nexperia.com/documents/data-sheet/74HC_HCT165.pdf",+ "file": "docs/74hc165d-datasheet.pdf"+ }+ } }, "license": "CC-BY-SA-4.0",- "title": "74HC165D",- "org": "adom"-}+ "title": "74HC165D"+}