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74HC165D-JSM
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JSMSEMI Shift Registers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# 74HC165D-JSM++**JSMSEMI** · Shift Registers · SOP-16++74HC165D-JSM from JSMSEMI, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | SH/LD | input | Shift/Load control input; LOW loads parallel inputs A-H into the register, HIGH enables serial shift operation on the rising clock edge. |+| 2 | CLK | input | Clock input; register shifts on rising edge when SH/LD is HIGH and CLK INH is LOW; interchangeable with CLK INH. |+| 3 | E | input | Parallel data input E; loaded into the fifth register stage when SH/LD is LOW (parallel load). |+| 4 | F | input | Parallel data input F; loaded into the sixth register stage when SH/LD is LOW (parallel load). |+| 5 | G | input | Parallel data input G; loaded into the seventh register stage when SH/LD is LOW (parallel load). |+| 6 | H | input | Parallel data input H; loaded into the eighth (last) register stage when SH/LD is LOW (parallel load). |+| 7 | ~QH | output | Complementary serial output; inverted QH from the last shift-register stage; can drive up to 10 LSTTL loads. |+| 8 | GND | power_in | Ground reference; 0 V supply rail. |+| 9 | QH | output | Serial data output; data from the last (H) register stage shifted out MSB-first; can drive up to 10 LSTTL loads. |+| 10 | SER | input | Serial data input; data present at SER is shifted into the first register stage on each rising clock edge during shift operation. |+| 11 | A | input | Parallel data input A; loaded into the first register stage when SH/LD is LOW (parallel load). |+| 12 | B | input | Parallel data input B; loaded into the second register stage when SH/LD is LOW (parallel load). |+| 13 | C | input | Parallel data input C; loaded into the third register stage when SH/LD is LOW (parallel load). |+| 14 | D | input | Parallel data input D; loaded into the fourth register stage when SH/LD is LOW (parallel load). |+| 15 | CLK INH | input | Clock inhibit input; HIGH level inhibits all clock transitions; LOW level allows clocking; interchangeable with CLK. |+| 16 | VCC | power_in | Positive supply voltage; recommended operating range 2 V to 6 V; absolute maximum -0.5 V to 7 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | JSMSEMI |+| Package | SOP-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `74HC165D-JSM`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOP-16 (KiCad packages3D, STEP)+- 3D model files: `74hc165d-jsm-etched.step` / `74hc165d-jsm-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74hc165d-jsm.step` / `74hc165d-jsm.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [JSMSEMI datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603384067861585920) (9 pp, sha256 `965241d5bb3d7d44`, retrieved 2026-09-17, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-sonnet-4-6` (vision), consensus `claude-opus-4-7` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/74hc165d-jsm-datasheet.pdf)
page.jsonadded+191@@ -0,0 +1,191 @@+{+ "slug": "74hc165d-jsm",+ "version": "0.1.0",+ "type": "component",+ "description": "JSMSEMI Shift Registers, SOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "74hc165d-jsm",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "74hc165d-jsm.kicad_sym",+ "74hc165d-jsm.kicad_mod",+ "74hc165d-jsm.glb",+ "74hc165d-jsm.step",+ "74hc165d-jsm.lbr",+ "docs/hero.png",+ "docs/74hc165d-jsm-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "74HC165D-JSM",+ "manufacturer": "JSMSEMI",+ "package": "SOP-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Shift Registers",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603384067861585920",+ "parts": {+ "symbol": "74hc165d-jsm.kicad_sym",+ "footprint": "74hc165d-jsm.kicad_mod",+ "model_3d": "74hc165d-jsm-etched.glb",+ "model_3d_plain": "74hc165d-jsm.glb",+ "model_3d_step": "74hc165d-jsm-etched.step",+ "model_3d_step_plain": "74hc165d-jsm.step",+ "lbr": "74hc165d-jsm.lbr"+ },+ "distributor_links": {+ "lcsc": "C22447130"+ },+ "pins": [+ {+ "number": "1",+ "name": "SH/LD",+ "type": "input",+ "description": "Shift/Load control input; LOW loads parallel inputs A-H into the register, HIGH enables serial shift operation on the rising clock edge."+ },+ {+ "number": "2",+ "name": "CLK",+ "type": "input",+ "description": "Clock input; register shifts on rising edge when SH/LD is HIGH and CLK INH is LOW; interchangeable with CLK INH."+ },+ {+ "number": "3",+ "name": "E",+ "type": "input",+ "description": "Parallel data input E; loaded into the fifth register stage when SH/LD is LOW (parallel load)."+ },+ {+ "number": "4",+ "name": "F",+ "type": "input",+ "description": "Parallel data input F; loaded into the sixth register stage when SH/LD is LOW (parallel load)."+ },+ {+ "number": "5",+ "name": "G",+ "type": "input",+ "description": "Parallel data input G; loaded into the seventh register stage when SH/LD is LOW (parallel load)."+ },+ {+ "number": "6",+ "name": "H",+ "type": "input",+ "description": "Parallel data input H; loaded into the eighth (last) register stage when SH/LD is LOW (parallel load)."+ },+ {+ "number": "7",+ "name": "~QH",+ "type": "output",+ "description": "Complementary serial output; inverted QH from the last shift-register stage; can drive up to 10 LSTTL loads."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference; 0 V supply rail."+ },+ {+ "number": "9",+ "name": "QH",+ "type": "output",+ "description": "Serial data output; data from the last (H) register stage shifted out MSB-first; can drive up to 10 LSTTL loads."+ },+ {+ "number": "10",+ "name": "SER",+ "type": "input",+ "description": "Serial data input; data present at SER is shifted into the first register stage on each rising clock edge during shift operation."+ },+ {+ "number": "11",+ "name": "A",+ "type": "input",+ "description": "Parallel data input A; loaded into the first register stage when SH/LD is LOW (parallel load)."+ },+ {+ "number": "12",+ "name": "B",+ "type": "input",+ "description": "Parallel data input B; loaded into the second register stage when SH/LD is LOW (parallel load)."+ },+ {+ "number": "13",+ "name": "C",+ "type": "input",+ "description": "Parallel data input C; loaded into the third register stage when SH/LD is LOW (parallel load)."+ },+ {+ "number": "14",+ "name": "D",+ "type": "input",+ "description": "Parallel data input D; loaded into the fourth register stage when SH/LD is LOW (parallel load)."+ },+ {+ "number": "15",+ "name": "CLK INH",+ "type": "input",+ "description": "Clock inhibit input; HIGH level inhibits all clock transitions; LOW level allows clocking; interchangeable with CLK."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage; recommended operating range 2 V to 6 V; absolute maximum -0.5 V to 7 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-sonnet-4-6",+ "primary_mode": "vision",+ "consensus_model": "claude-opus-4-7",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "vision extraction: provenance cannot be text-verified; needs consensus"+ ],+ "pages_sent": 9,+ "cost_usd": 0.1966,+ "at": "2026-09-17T23:15:59"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603384067861585920",+ "pages": 9,+ "sha256": "965241d5bb3d7d44",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}