component
74HC165D-JSM
Public Made by Adomby adom
JSMSEMI Shift Registers, SOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdown74HC165D-JSM
JSMSEMI · Shift Registers · SOP-16
74HC165D-JSM from JSMSEMI, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SH/LD | input | Shift/Load control input; LOW loads parallel inputs A-H into the register, HIGH enables serial shift operation on the rising clock edge. |
| 2 | CLK | input | Clock input; register shifts on rising edge when SH/LD is HIGH and CLK INH is LOW; interchangeable with CLK INH. |
| 3 | E | input | Parallel data input E; loaded into the fifth register stage when SH/LD is LOW (parallel load). |
| 4 | F | input | Parallel data input F; loaded into the sixth register stage when SH/LD is LOW (parallel load). |
| 5 | G | input | Parallel data input G; loaded into the seventh register stage when SH/LD is LOW (parallel load). |
| 6 | H | input | Parallel data input H; loaded into the eighth (last) register stage when SH/LD is LOW (parallel load). |
| 7 | ~QH | output | Complementary serial output; inverted QH from the last shift-register stage; can drive up to 10 LSTTL loads. |
| 8 | GND | power_in | Ground reference; 0 V supply rail. |
| 9 | QH | output | Serial data output; data from the last (H) register stage shifted out MSB-first; can drive up to 10 LSTTL loads. |
| 10 | SER | input | Serial data input; data present at SER is shifted into the first register stage on each rising clock edge during shift operation. |
| 11 | A | input | Parallel data input A; loaded into the first register stage when SH/LD is LOW (parallel load). |
| 12 | B | input | Parallel data input B; loaded into the second register stage when SH/LD is LOW (parallel load). |
| 13 | C | input | Parallel data input C; loaded into the third register stage when SH/LD is LOW (parallel load). |
| 14 | D | input | Parallel data input D; loaded into the fourth register stage when SH/LD is LOW (parallel load). |
| 15 | CLK INH | input | Clock inhibit input; HIGH level inhibits all clock transitions; LOW level allows clocking; interchangeable with CLK. |
| 16 | VCC | power_in | Positive supply voltage; recommended operating range 2 V to 6 V; absolute maximum -0.5 V to 7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | JSMSEMI |
| Package | SOP-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
74HC165D-JSM - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files:
74hc165d-jsm-etched.step/74hc165d-jsm-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc165d-jsm.step/74hc165d-jsm.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: JSMSEMI datasheet (9 pp, sha256
965241d5bb3d7d44, retrieved 2026-09-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-sonnet-4-6(vision), consensusclaude-opus-4-7(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).