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74HC165BQ

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Nexperia Shift Registers, DHVQFN-16-EP(2.5x3.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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74HC165BQ

Nexperia · Shift Registers · DHVQFN-16-EP(2.5x3.5)

74HC165BQ from Nexperia, in a DHVQFN-16-EP(2.5x3.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PL input Asynchronous parallel load input, active LOW; when LOW, data on D0 to D7 is loaded into the shift register asynchronously.
2 CP input Clock input, edge-triggered on the LOW-to-HIGH transition; data is shifted on this edge when CE is LOW.
3 D4 input Parallel data input D4 (Dn), loaded into the register when PL is LOW.
4 D5 input Parallel data input D5 (Dn), loaded into the register when PL is LOW.
5 D6 input Parallel data input D6 (Dn), loaded into the register when PL is LOW.
6 D7 input Parallel data input D7 (Dn), loaded into the register when PL is LOW.
7 Q7 output Complementary output from the last stage of the shift register.
8 GND power_in Ground (0 V).
9 Q7 output Serial output from the last stage of the shift register.
10 DS input Serial data input; data enters the register serially at DS when PL is HIGH.
11 D0 input Parallel data input D0 (Dn), loaded into the register when PL is LOW.
12 D1 input Parallel data input D1 (Dn), loaded into the register when PL is LOW.
13 D2 input Parallel data input D2 (Dn), loaded into the register when PL is LOW.
14 D3 input Parallel data input D3 (Dn), loaded into the register when PL is LOW.
15 CE input Clock enable input, active LOW; a HIGH on CE disables the CP input.
16 VCC power_in Positive supply voltage; 2.0 V to 6.0 V for 74HC165 (Table 5).
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Nexperia
Package DHVQFN-16-EP(2.5x3.5)
Category Logic
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 5
Input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 5
Output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 5
Output current IO -25 25 mA -0.5 V < VO < VCC + 0.5 V 5
Supply current ICC 50 mA 5
Ground current IGND -50 mA 5
Storage temperature Tstg -65 150 °C 5
Total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 5
Supply voltage VCC 2 5 6 V 5
Ambient temperature Tamb -40 125 °C 5
Input transition rise and fall rate Δt/ΔV 625 ns/V VCC = 2.0 V 5
Input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 5
Input transition rise and fall rate Δt/ΔV 83 ns/V VCC = 6.0 V 5
HIGH-level input voltage VIH 1.5 1.2 V VCC = 2.0 V 5
HIGH-level input voltage VIH 3.15 2.4 V VCC = 4.5 V 5
HIGH-level input voltage VIH 4.2 3.2 V VCC = 6.0 V 5
LOW-level input voltage VIL 0.8 0.5 V VCC = 2.0 V 5
LOW-level input voltage VIL 2.1 1.35 V VCC = 4.5 V 5
HIGH-level output voltage VOH 1.9 2 V IO = -20 μA; VCC = 2.0 V 6
HIGH-level output voltage VOH 4.4 4.5 V IO = -20 μA; VCC = 4.5 V 6
HIGH-level output voltage VOH 5.9 6 V IO = -20 μA; VCC = 6.0 V 6
HIGH-level output voltage VOH 3.7 4.32 V IO = -4.0 mA; VCC = 4.5 V 6
HIGH-level output voltage VOH 5.2 5.81 V IO = -5.2 mA; VCC = 6.0 V 6
LOW-level output voltage VOL 0 0.1 V IO = 20 μA; VCC = 2.0 V 6
LOW-level output voltage VOL 0.15 0.4 V IO = 4.0 mA; VCC = 4.5 V 6
LOW-level output voltage VOL 0.16 0.4 V IO = 5.2 mA; VCC = 6.0 V 6
Input leakage current II -1 1 μA VI = VCC or GND; VCC = 6.0 V 6
Supply current ICC 160 μA VI = VCC or GND; IO = 0 A; VCC = 6.0 V 6
Input capacitance CI 3.5 pF 6
Propagation delay tpd 52 250 ns VCC = 2.0 V; CP or CE to Q7, Q7; see Fig. 5 7
Propagation delay tpd 19 50 ns VCC = 4.5 V; CP or CE to Q7, Q7; see Fig. 5 7
Propagation delay tpd 15 43 ns VCC = 6.0 V; CP or CE to Q7, Q7; see Fig. 5 7
Propagation delay tpd 50 250 ns VCC = 2.0 V; PL to Q7, Q7; see Fig. 6 7
Propagation delay tpd 18 50 ns VCC = 4.5 V; PL to Q7, Q7; see Fig. 6 7
Propagation delay tpd 14 43 ns VCC = 6.0 V; PL to Q7, Q7; see Fig. 6 7
Propagation delay tpd 36 180 ns VCC = 2.0 V; D7 to Q7, Q7; see Fig. 7 7
Propagation delay tpd 13 36 ns VCC = 4.5 V; D7 to Q7, Q7; see Fig. 7 7
Propagation delay tpd 10 31 ns VCC = 6.0 V; D7 to Q7, Q7; see Fig. 7 7
Transition time tt 19 110 ns VCC = 2.0 V; Q7, Q7 output; see Fig. 5 7
Transition time tt 7 22 ns VCC = 4.5 V; Q7, Q7 output; see Fig. 5 7
Transition time tt 6 19 ns VCC = 6.0 V; Q7, Q7 output; see Fig. 5 7
Pulse width tW 120 17 ns VCC = 2.0 V; CP input HIGH or LOW; see Fig. 5 7
Pulse width tW 24 6 ns VCC = 4.5 V; CP input HIGH or LOW; see Fig. 5 7
Pulse width tW 20 5 ns VCC = 6.0 V; CP input HIGH or LOW; see Fig. 5 7
Pulse width tW 120 14 ns VCC = 2.0 V; PL input LOW; see Fig. 6 7
Pulse width tW 24 5 ns VCC = 4.5 V; PL input LOW; see Fig. 6 7
Pulse width tW 20 4 ns VCC = 6.0 V; PL input LOW; see Fig. 6 7
Recovery time trec 150 22 ns VCC = 2.0 V; PL to CP, CE; see Fig. 6 7
Recovery time trec 30 8 ns VCC = 4.5 V; PL to CP, CE; see Fig. 6 7
Recovery time trec 26 6 ns VCC = 6.0 V; PL to CP, CE; see Fig. 6 7
Set-up time tsu 120 22 ns VCC = 2.0 V; Dn to PL; see Fig. 9 8
Set-up time tsu 24 8 ns VCC = 4.5 V; Dn to PL; see Fig. 9 8
Set-up time tsu 20 6 ns VCC = 6.0 V; Dn to PL; see Fig. 9 8
Maximum frequency fmax 4 17 MHz VCC = 2.0 V; CP input; see Fig. 5 7
Maximum frequency fmax 20 51 MHz VCC = 4.5 V; CP input; see Fig. 5 7
Maximum frequency fmax 24 61 MHz VCC = 6.0 V; CP input; see Fig. 5 7

CAD (KiCad official)

  • Symbol: 74HC165BQ
  • Footprint: Package_DFN_QFN:DHVQFN-16-1EP_2.5x3.5mm_P0.5mm_EP1x2mm
  • 3D model: DHVQFN-16-EP(2.5x3.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: 74hc165bq-etched.step / 74hc165bq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc165bq.step / 74hc165bq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (18 pp, sha256 376fad78107f38d0, retrieved 2026-10-16, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF