74HC165-HXY

{
  "slug": "74hc165-hxy",
  "version": "0.1.0",
  "type": "component",
  "description": "HXY MOSFET Shift Registers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
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    "logic",
    "74hc165-hxy",
    "factory-2.0.0",
    "extractor-text"
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  "dependencies": {},
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  "component": {
    "mpn": "74HC165-HXY",
    "manufacturer": "HXY MOSFET",
    "package": "SOP-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Shift Registers",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590905601453617152",
    "parts": {
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      "lbr": "74hc165-hxy.lbr"
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    "distributor_links": {
      "lcsc": "C7427351"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T09:26:56Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "PL",
        "type": "input",
        "description": "Asynchronous parallel load input, active LOW: when LOW, data on D0 to D7 is loaded into the shift register asynchronously."
      },
      {
        "number": "2",
        "name": "CP",
        "type": "input",
        "description": "Clock input, edge-triggered on the LOW-to-HIGH transition; data is shifted on these transitions when CE is LOW, and a HIGH on CE disables CP."
      },
      {
        "number": "3",
        "name": "D4",
        "type": "input",
        "description": "Parallel data input D4, loaded into the register when PL is LOW; inputs are overvoltage tolerant to 15 V."
      },
      {
        "number": "4",
        "name": "D5",
        "type": "input",
        "description": "Parallel data input D5, loaded into the register when PL is LOW; inputs are overvoltage tolerant to 15 V."
      },
      {
        "number": "5",
        "name": "D6",
        "type": "input",
        "description": "Parallel data input D6, loaded into the register when PL is LOW; inputs are overvoltage tolerant to 15 V."
      },
      {
        "number": "6",
        "name": "D7",
        "type": "input",
        "description": "Parallel data input D7, loaded into the register when PL is LOW; inputs are overvoltage tolerant to 15 V."
      },
      {
        "number": "7",
        "name": "Q7",
        "type": "output",
        "description": "Complementary (inverted) output of the last register stage; pin 7 is the complement output, pin 9 is the true output."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference, 0 V."
      },
      {
        "number": "9",
        "name": "Q7",
        "type": "output",
        "description": "Serial (true) output of the last register stage."
      },
      {
        "number": "10",
        "name": "DS",
        "type": "input",
        "description": "Serial data input, shifted into the register on the CP LOW-to-HIGH transition when PL is HIGH and CE is LOW; inputs are overvoltage tolerant to 15 V."
      },
      {
        "number": "11",
        "name": "D0",
        "type": "input",
        "description": "Parallel data input D0, loaded into the register when PL is LOW; inputs are overvoltage tolerant to 15 V."
      },
      {
        "number": "12",
        "name": "D1",
        "type": "input",
        "description": "Parallel data input D1, loaded into the register when PL is LOW; inputs are overvoltage tolerant to 15 V."
      },
      {
        "number": "13",
        "name": "D2",
        "type": "input",
        "description": "Parallel data input D2, loaded into the register when PL is LOW; inputs are overvoltage tolerant to 15 V."
      },
      {
        "number": "14",
        "name": "D3",
        "type": "input",
        "description": "Parallel data input D3, loaded into the register when PL is LOW; inputs are overvoltage tolerant to 15 V."
      },
      {
        "number": "15",
        "name": "CE",
        "type": "input",
        "description": "Clock enable input, active LOW: data is shifted only when CE is LOW, and a HIGH disables the CP input."
      },
      {
        "number": "16",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply voltage: 2.0 V to 6.0 V for 74HC165 and 4.5 V to 5.5 V for 74HCT165 per the recommended operating conditions."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The text extraction dropped the overbar, so pins 7 and 9 both read 'Q7'. Pin 7 is the complementary ; The datasheet gives one pin table (page 4) that covers DIP16, SOP16 and TSSOP16 together. The SOP16 ; The datasheet covers both the 74HC165 (CMOS input levels) and 74HCT165 (TTL input levels). The pinou"
        ],
        "pages_sent": 19,
        "cost_usd": 0.0746,
        "at": "2026-10-18T09:24:59"
      },
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        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590905601453617152",
        "pages": 19,
        "sha256": "41ced16222e9c961",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
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}