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74HC164M

Public Made by Adom

by adom

HGSEMI Shifting Register, SOIC-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs 74hc164m: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers 74hc164m: viewers · Ray 1mo ago
74hc164m-etched.fit.json 74hc164m: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
74hc164m-etched.glb 74hc164m: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
74hc164m-etched.step 74hc164m: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
74hc164m.glb Publish 0.1.0 · Ray 1mo ago
74hc164m.kicad_mod Publish 0.1.0 · Ray 1mo ago
74hc164m.kicad_sym Publish 0.1.0 · Ray 1mo ago
74hc164m.lbr Publish 0.1.0 · Ray 1mo ago
74hc164m.step Publish 0.1.0 · Ray 1mo ago
package.json Publish 0.1.0 · Ray 1mo ago
page.json 74hc164m: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 27d ago
README.md 74hc164m: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago

74HC164M

HGSEMI · Shifting Register · SOIC-14

74HC164M from HGSEMI, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A input Serial data input A. Internally ANDed with input B to feed the first stage of the shift register; sampled on the rising edge of CLOCK.
2 B input Serial data input B. Internally ANDed with input A to feed the first stage of the shift register; sampled on the rising edge of CLOCK.
3 QA output Parallel data output stage A (first stage of the shift register).
4 QB output Parallel data output stage B.
5 QC output Parallel data output stage C.
6 QD output Parallel data output stage D.
7 GND power_in Ground / power supply return (0 V reference).
8 CLOCK input Shift clock input. On each rising edge the eight register bits shift right one position and the A·B product is loaded into QA. Minimum pulse width 18 ns (typ).
9 CLEAR input Active-low asynchronous clear. Driving this pin low forces all outputs QA-QH to logic 0 regardless of CLOCK.
10 QE output Parallel data output stage E.
11 QF output Parallel data output stage F.
12 QG output Parallel data output stage G.
13 QH output Parallel data output stage H (last stage of the shift register; used as serial-out for cascading).
14 VCC power_in Positive supply, 2.0 V to 6.0 V (absolute max 6.5 V).

Key specifications

Parameter Value
Manufacturer HGSEMI
Package SOIC-14
Category Logic
Pins 14

Ordering variants

Same part, different packaging or reel option.

  • 74HC164MN
  • 74HC164MM/TR
  • 74HC164MMT/TR
  • 74HC164MLQ/TR

CAD (KiCad official)

  • Symbol: 74HC164M
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: 74hc164m-etched.step / 74hc164m-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc164m.step / 74hc164m.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HGSEMI datasheet (8 pp, sha256 c4cbc1a54be27507, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF