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74hc164m: factory component page (tier=lcsc)

Ray ·77cf2aeb55 ·1mo ago ·parent 6c16524
1 file changed +170−8
page.json+170−8
@@ -1,13 +1,180 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "74hc164m",+  "title": "74HC164M",+  "brief": "HGSEMI Shifting Register, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "version": "0.1.0",-  "type": "component",-  "description": "HGSEMI Shifting Register, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "logic",     "74hc164m"   ],+  "component": {+    "mpn": "74HC164M",+    "manufacturer": "HGSEMI",+    "package": "SOIC-14",+    "pin_count": 14,+    "category": "Logic",+    "subcategory": "Shifting Register",+    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/c42157c966be2f3f5c045823f7bffc69.pdf",+    "parts": {+      "symbol": "74hc164m.kicad_sym",+      "footprint": "74hc164m.kicad_mod",+      "model_3d": "74hc164m.glb",+      "model_3d_step": "74hc164m.step",+      "lbr": "74hc164m.lbr"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "A",+        "type": "input",+        "description": "Serial data input A. Internally ANDed with input B to feed the first stage of the shift register; sampled on the rising edge of CLOCK."+      },+      {+        "number": "2",+        "name": "B",+        "type": "input",+        "description": "Serial data input B. Internally ANDed with input A to feed the first stage of the shift register; sampled on the rising edge of CLOCK."+      },+      {+        "number": "3",+        "name": "QA",+        "type": "output",+        "description": "Parallel data output stage A (first stage of the shift register)."+      },+      {+        "number": "4",+        "name": "QB",+        "type": "output",+        "description": "Parallel data output stage B."+      },+      {+        "number": "5",+        "name": "QC",+        "type": "output",+        "description": "Parallel data output stage C."+      },+      {+        "number": "6",+        "name": "QD",+        "type": "output",+        "description": "Parallel data output stage D."+      },+      {+        "number": "7",+        "name": "GND",+        "type": "power_in",+        "description": "Ground / power supply return (0 V reference)."+      },+      {+        "number": "8",+        "name": "CLOCK",+        "type": "input",+        "description": "Shift clock input. On each rising edge the eight register bits shift right one position and the A\u00b7B product is loaded into QA. Minimum pulse width 18 ns (typ)."+      },+      {+        "number": "9",+        "name": "CLEAR",+        "type": "input",+        "description": "Active-low asynchronous clear. Driving this pin low forces all outputs QA-QH to logic 0 regardless of CLOCK."+      },+      {+        "number": "10",+        "name": "QE",+        "type": "output",+        "description": "Parallel data output stage E."+      },+      {+        "number": "11",+        "name": "QF",+        "type": "output",+        "description": "Parallel data output stage F."+      },+      {+        "number": "12",+        "name": "QG",+        "type": "output",+        "description": "Parallel data output stage G."+      },+      {+        "number": "13",+        "name": "QH",+        "type": "output",+        "description": "Parallel data output stage H (last stage of the shift register; used as serial-out for cascading)."+      },+      {+        "number": "14",+        "name": "VCC",+        "type": "power_in",+        "description": "Positive supply, 2.0 V to 6.0 V (absolute max 6.5 V)."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://datasheet.lcsc.com/datasheet/pdf/c42157c966be2f3f5c045823f7bffc69.pdf",+        "pages": 8,+        "sha256": "c4cbc1a54be27507",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 14,+        "described": 14,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Manufacturer": "HGSEMI",+      "Package": "SOIC-14",+      "Category": "Logic",+      "Pins": "14"+    }+  },+  "variants": [+    {+      "mpn": "74HC164MN",+      "kind": "packaging"+    },+    {+      "mpn": "74HC164MM/TR",+      "kind": "packaging"+    },+    {+      "mpn": "74HC164MMT/TR",+      "kind": "packaging"+    },+    {+      "mpn": "74HC164MLQ/TR",+      "kind": "packaging"+    }+  ],+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "74hc164m"+  ],+  "discovery_pitch": "74HC164M (HGSEMI) component page with datasheet-verified CAD.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -25,10 +192,5 @@     "docs/74hc164m-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file