component
74HC161S
Public Made by Adomby adom
GR Counters, Dividers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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74HC161S
GR · Counters, Dividers · SOP-16
74HC161S from GR, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MR | input | Asynchronous active-low master reset: when MR is low, all outputs Q0-Q3 and TC are forced low regardless of the clock; per note 3, MR may only go low-to-high while CP is held high. |
| 2 | CP | input | Clock input; the counter is clocked on the rising edge of CP, and per note 2 PE or TE may only switch high-to-low while CP is held high. |
| 3 | P0 | input | Parallel data input for bit 0, loaded to output Q0 when the parallel-load mode is selected (SPE, see truth table). |
| 4 | P1 | input | Parallel data input for bit 1, loaded to output Q1 when the parallel-load mode is selected (SPE, see truth table). |
| 5 | P2 | input | Parallel data input for bit 2, loaded to output Q2 when the parallel-load mode is selected (SPE, see truth table). |
| 6 | P3 | input | Parallel data input for bit 3, loaded to output Q3 when the parallel-load mode is selected (SPE, see truth table). |
| 7 | PE | input | Output count-enable control, active low per datasheet; used together with TE to select continuous counting or stop/hold, and may only switch high-to-low while CP is high. |
| 8 | GND | power_in | Power supply ground. |
| 9 | SPE | input | Parallel data enable control that selects parallel data transfer to the outputs; per note 3, SPE may only go low-to-high while CP is held high. |
| 10 | TE | input | Output count-enable control, active low per datasheet; used together with PE for continuous counting or hold, and may only switch high-to-low while CP is high. |
| 11 | Q3 | output | Data/count output for bit 3. |
| 12 | Q2 | output | Data/count output for bit 2. |
| 13 | Q1 | output | Data/count output for bit 1. |
| 14 | Q0 | output | Data/count output for bit 0. |
| 15 | TC | output | Carry output flag for cascading multiple devices; TC goes high only when TE and all Qn outputs are high. |
| 16 | VCC | power_in | Positive power supply; operating voltage 2.0 V to 6.0 V per the datasheet (recommended 2 V to 6 V, absolute maximum VCC -0.5 to 6.5 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GR |
| Package | SOP-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (absolute maximum) | VCC | -0.5 | 6.5 | V | 1 | ||
| Input/output voltage (absolute maximum) | VIN、VOUT | -0.5 | V | 1 | |||
| Input/output clamp current | IIK、IOK | -20 | 20 | mA | 1 | ||
| Continuous output current per pin | IOUT | -25 | 25 | mA | 1 | ||
| Continuous current through VCC or GND | ICC、IGND | -50 | 50 | mA | 1 | ||
| Power dissipation | PD | 500 | mW | 1 | |||
| Operating temperature | TA | 0 | 70 | ℃ | 1 | ||
| Storage temperature | TS | -65 | 150 | ℃ | 1 | ||
| Lead soldering temperature | TW | 260 | ℃ | 10s | 2 | ||
| Operating supply voltage (recommended) | VCC | 2 | 5 | 6 | V | 3 | |
| Input/output voltage (recommended) | VIN、Vout | 0 | V | 3 | |||
| Input rise and fall time | tr、tf | 0 | 1000 | ns | VCC=2.0V | 3 | |
| Input rise and fall time | tr、tf | 0 | 500 | ns | VCC=4.5V | 3 | |
| Input rise and fall time | tr、tf | 0 | 400 | ns | VCC=6.0V | 3 | |
| High-level input voltage | VIH | 1.5 | V | TA=25℃; VCC=2.0V | 4 | ||
| High-level input voltage | VIH | 3.15 | V | TA=25℃; VCC=4.5V | 4 | ||
| High-level input voltage | VIH | 4.2 | V | TA=25℃; VCC=6.0V | 4 | ||
| Low-level input voltage | VIL | 0.5 | V | TA=25℃; VCC=2.0V | 4 | ||
| Low-level input voltage | VIL | 1.35 | V | TA=25℃; VCC=4.5V | 4 | ||
| Low-level input voltage | VIL | 1.8 | V | TA=25℃; VCC=6.0V | 4 | ||
| High-level output voltage | VOH | 1.9 | V | TA=25℃; VI=VIH or VIL; IOH=20µA; VCC=2.0V | 4 | ||
| High-level output voltage | VOH | 4.4 | V | TA=25℃; VI=VIH or VIL; IOH=20µA; VCC=4.5V | 4 | ||
| High-level output voltage | VOH | 5.9 | V | TA=25℃; VI=VIH or VIL; IOH=20µA; VCC=6.0V | 4 | ||
| High-level output voltage | VOH | 4 | 4.4 | V | TA=25℃; IOH=4.0mA; VCC=4.5V | 4 | |
| High-level output voltage | VOH | 5.5 | 5.9 | V | TA=25℃; IOH=5.2mA; VCC=6.0V | 4 | |
| Low-level output voltage | VOL | 0.1 | V | TA=25℃; VI=VIH or VIL; IOH=20µA; VCC=2.0V | 4 | ||
| Low-level output voltage | VOL | 0.07 | 0.3 | V | TA=25℃; VI=VIH or VIL; IOH=4.0mA; VCC=4.5V | 4 | |
| Low-level output voltage | VOL | 0.08 | 0.3 | V | TA=25℃; VI=VIH or VIL; IOH=5.2mA; VCC=6.0V | 4 | |
| Input current | IIN | 1 | uA | TA=25℃; VI=VCC or GND; VCC=6.0V | 4 | ||
| Operating current | ICC | 0.04 | 8 | uA | TA=25℃; VI=VCC or GND; IOUT=0µA; VCC=6.0V | 4 | |
| Operating voltage (DC table) | VCC | 2 | 6 | V | TA=25℃ | 4 | |
| Clock frequency | fmax | 0 | 20 | MHz | VCC=5.0V; CL=16pF; tr=tf≤20ns; Ta=25℃ | 5 | |
| MR to CP minimum removal time | tREM | 20 | ns | VCC=5.0V; CL=16pF; tr=tf≤20ns; Ta=25℃ | 5 | ||
| SPE, enables or data to CP minimum setup time | tSU | 20 | ns | VCC=5.0V; CL=16pF; tr=tf≤20ns; Ta=25℃ | 5 | ||
| SPE, enables or data to CP minimum hold time | tH | 5 | ns | VCC=5.0V; CL=16pF; tr=tf≤20ns; Ta=25℃ | 5 | ||
| CP, MR or SPE minimum pulse width | tW | 20 | ns | VCC=5.0V; CL=16pF; tr=tf≤20ns; Ta=25℃ | 5 |
CAD (KiCad official)
- Symbol:
74HC161S - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files:
74hc161s-etched.step/74hc161s-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc161s.step/74hc161s.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: GR datasheet (6 pp, sha256
e660328365ef1642, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 74HC161S
**GR** · Counters, Dividers · SOP-16
74HC161S from GR, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MR | input | Asynchronous active-low master reset: when MR is low, all outputs Q0-Q3 and TC are forced low regardless of the clock; per note 3, MR may only go low-to-high while CP is held high. |
| 2 | CP | input | Clock input; the counter is clocked on the rising edge of CP, and per note 2 PE or TE may only switch high-to-low while CP is held high. |
| 3 | P0 | input | Parallel data input for bit 0, loaded to output Q0 when the parallel-load mode is selected (SPE, see truth table). |
| 4 | P1 | input | Parallel data input for bit 1, loaded to output Q1 when the parallel-load mode is selected (SPE, see truth table). |
| 5 | P2 | input | Parallel data input for bit 2, loaded to output Q2 when the parallel-load mode is selected (SPE, see truth table). |
| 6 | P3 | input | Parallel data input for bit 3, loaded to output Q3 when the parallel-load mode is selected (SPE, see truth table). |
| 7 | PE | input | Output count-enable control, active low per datasheet; used together with TE to select continuous counting or stop/hold, and may only switch high-to-low while CP is high. |
| 8 | GND | power_in | Power supply ground. |
| 9 | SPE | input | Parallel data enable control that selects parallel data transfer to the outputs; per note 3, SPE may only go low-to-high while CP is held high. |
| 10 | TE | input | Output count-enable control, active low per datasheet; used together with PE for continuous counting or hold, and may only switch high-to-low while CP is high. |
| 11 | Q3 | output | Data/count output for bit 3. |
| 12 | Q2 | output | Data/count output for bit 2. |
| 13 | Q1 | output | Data/count output for bit 1. |
| 14 | Q0 | output | Data/count output for bit 0. |
| 15 | TC | output | Carry output flag for cascading multiple devices; TC goes high only when TE and all Qn outputs are high. |
| 16 | VCC | power_in | Positive power supply; operating voltage 2.0 V to 6.0 V per the datasheet (recommended 2 V to 6 V, absolute maximum VCC -0.5 to 6.5 V). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GR |
| Package | SOP-16 |
| Category | Logic |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (absolute maximum) | VCC | -0.5 | | 6.5 | V | | 1 |
| Input/output voltage (absolute maximum) | VIN、VOUT | -0.5 | | | V | | 1 |
| Input/output clamp current | IIK、IOK | -20 | | 20 | mA | | 1 |
| Continuous output current per pin | IOUT | -25 | | 25 | mA | | 1 |
| Continuous current through VCC or GND | ICC、IGND | -50 | | 50 | mA | | 1 |
| Power dissipation | PD | | | 500 | mW | | 1 |
| Operating temperature | TA | 0 | | 70 | ℃ | | 1 |
| Storage temperature | TS | -65 | | 150 | ℃ | | 1 |
| Lead soldering temperature | TW | | | 260 | ℃ | 10s | 2 |
| Operating supply voltage (recommended) | VCC | 2 | 5 | 6 | V | | 3 |
| Input/output voltage (recommended) | VIN、Vout | 0 | | | V | | 3 |
| Input rise and fall time | tr、tf | 0 | | 1000 | ns | VCC=2.0V | 3 |
| Input rise and fall time | tr、tf | 0 | | 500 | ns | VCC=4.5V | 3 |
| Input rise and fall time | tr、tf | 0 | | 400 | ns | VCC=6.0V | 3 |
| High-level input voltage | VIH | 1.5 | | | V | TA=25℃; VCC=2.0V | 4 |
| High-level input voltage | VIH | 3.15 | | | V | TA=25℃; VCC=4.5V | 4 |
| High-level input voltage | VIH | 4.2 | | | V | TA=25℃; VCC=6.0V | 4 |
| Low-level input voltage | VIL | | | 0.5 | V | TA=25℃; VCC=2.0V | 4 |
| Low-level input voltage | VIL | | | 1.35 | V | TA=25℃; VCC=4.5V | 4 |
| Low-level input voltage | VIL | | | 1.8 | V | TA=25℃; VCC=6.0V | 4 |
| High-level output voltage | VOH | 1.9 | | | V | TA=25℃; VI=VIH or VIL; IOH=20µA; VCC=2.0V | 4 |
| High-level output voltage | VOH | 4.4 | | | V | TA=25℃; VI=VIH or VIL; IOH=20µA; VCC=4.5V | 4 |
| High-level output voltage | VOH | 5.9 | | | V | TA=25℃; VI=VIH or VIL; IOH=20µA; VCC=6.0V | 4 |
| High-level output voltage | VOH | 4 | 4.4 | | V | TA=25℃; IOH=4.0mA; VCC=4.5V | 4 |
| High-level output voltage | VOH | 5.5 | 5.9 | | V | TA=25℃; IOH=5.2mA; VCC=6.0V | 4 |
| Low-level output voltage | VOL | | | 0.1 | V | TA=25℃; VI=VIH or VIL; IOH=20µA; VCC=2.0V | 4 |
| Low-level output voltage | VOL | | 0.07 | 0.3 | V | TA=25℃; VI=VIH or VIL; IOH=4.0mA; VCC=4.5V | 4 |
| Low-level output voltage | VOL | | 0.08 | 0.3 | V | TA=25℃; VI=VIH or VIL; IOH=5.2mA; VCC=6.0V | 4 |
| Input current | IIN | | | 1 | uA | TA=25℃; VI=VCC or GND; VCC=6.0V | 4 |
| Operating current | ICC | | 0.04 | 8 | uA | TA=25℃; VI=VCC or GND; IOUT=0µA; VCC=6.0V | 4 |
| Operating voltage (DC table) | VCC | 2 | | 6 | V | TA=25℃ | 4 |
| Clock frequency | fmax | 0 | 20 | | MHz | VCC=5.0V; CL=16pF; tr=tf≤20ns; Ta=25℃ | 5 |
| MR to CP minimum removal time | tREM | 20 | | | ns | VCC=5.0V; CL=16pF; tr=tf≤20ns; Ta=25℃ | 5 |
| SPE, enables or data to CP minimum setup time | tSU | 20 | | | ns | VCC=5.0V; CL=16pF; tr=tf≤20ns; Ta=25℃ | 5 |
| SPE, enables or data to CP minimum hold time | tH | 5 | | | ns | VCC=5.0V; CL=16pF; tr=tf≤20ns; Ta=25℃ | 5 |
| CP, MR or SPE minimum pulse width | tW | 20 | | | ns | VCC=5.0V; CL=16pF; tr=tf≤20ns; Ta=25℃ | 5 |
## CAD (KiCad official)
- Symbol: `74HC161S`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files: `74hc161s-etched.step` / `74hc161s-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74hc161s.step` / `74hc161s.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [GR datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590922757955657728) (6 pp, sha256 `e660328365ef1642`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/74hc161s-datasheet.pdf)