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74HC161D

Public Made by Adom

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Nexperia Counters, Dividers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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74HC161D

Nexperia · Counters, Dividers · SOIC-16

74HC161D from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MR input Asynchronous master reset input (active LOW) that sets Q0 to Q3 LOW regardless of the levels on CP, PE, CET and CEP.
2 CP input Clock input that is edge-triggered on the LOW-to-HIGH transition, with all flip-flops clocked simultaneously.
3 D0 input Data input 0 that is loaded into the counter on the positive-going clock edge when PE is LOW.
4 D1 input Data input 1 that is loaded into the counter on the positive-going clock edge when PE is LOW.
5 D2 input Data input 2 that is loaded into the counter on the positive-going clock edge when PE is LOW.
6 D3 input Data input 3 that is loaded into the counter on the positive-going clock edge when PE is LOW.
7 CEP input Count enable input; both CEP and CET must be HIGH to count.
8 GND power_in Ground (0 V) reference for all voltages on the device.
9 PE input Parallel enable input (active LOW) that disables counting and loads data from D0 to D3 on the positive clock edge.
10 CET input Count enable carry input that is fed forward to enable the terminal count output TC.
11 Q3 output Flip-flop output Q3 of the 4-bit binary counter.
12 Q2 output Flip-flop output Q2 of the 4-bit binary counter.
13 Q1 output Flip-flop output Q1 of the 4-bit binary counter.
14 Q0 output Flip-flop output Q0 of the 4-bit binary counter.
15 TC output Terminal count output that goes HIGH when CET is HIGH and the counter is at terminal count (HHHH), used to enable the next cascaded stage.
16 VCC power_in Supply voltage, specified from 2.0 V to 6.0 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOIC-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC 2 5 6 V 7
ambient temperature Tamb -40 25 125 °C 7
input voltage VI 0 V 7
output voltage VO 0 V 7
input transition rise and fall rate Δt/ΔV 625 ns/V VCC = 2.0 V 7
input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 7
input transition rise and fall rate Δt/ΔV 83 ns/V VCC = 6.0 V 7
supply voltage VCC -0.5 7 V 6
input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 6
output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 6
output current IO -25 25 mA VO = -0.5 V to VCC + 0.5 V 6
supply current ICC 50 mA 6
ground current IGND -50 mA 6
storage temperature Tstg -65 150 °C 6
total power dissipation Ptot 500 mW 6
HIGH-level input voltage VIH 1.5 1.2 V VCC = 2.0 V 7
HIGH-level input voltage VIH 3.15 2.4 V VCC = 4.5 V 7
HIGH-level input voltage VIH 4.2 3.2 V VCC = 6.0 V 7
LOW-level input voltage VIL 0.8 0.5 V VCC = 2.0 V 7
LOW-level input voltage VIL 2.1 1.35 V VCC = 4.5 V 7
LOW-level input voltage VIL 2.8 1.8 V VCC = 6.0 V 7
HIGH-level output voltage VOH 1.9 2 V IO = -20 μA; VCC = 2.0 V 7
HIGH-level output voltage VOH 4.4 4.5 V IO = -20 μA; VCC = 4.5 V 7
HIGH-level output voltage VOH 5.9 6 V IO = -20 μA; VCC = 6.0 V 7
HIGH-level output voltage VOH 3.7 4.32 V IO = -4.0 mA; VCC = 4.5 V 7
HIGH-level output voltage VOH 5.2 5.81 V IO = -5.2 mA; VCC = 6.0 V 7
LOW-level output voltage VOL 0 0.1 V IO = 20 μA; VCC = 2.0 V 7
LOW-level output voltage VOL 0.15 0.4 V IO = 4.0 mA; VCC = 4.5 V 7
LOW-level output voltage VOL 0.16 0.4 V IO = 5.2 mA; VCC = 6.0 V 7
input leakage current II -1 1 μA VI = VCC or GND; VCC = 6.0 V 7
supply current ICC 160 μA VI = VCC or GND; IO = 0 A; VCC = 6.0 V 7
propagation delay CP to Qn tpd 61 285 ns VCC = 2.0 V; see Fig. 9 8
propagation delay CP to Qn tpd 22 57 ns VCC = 4.5 V; see Fig. 9 8
propagation delay CP to Qn tpd 18 48 ns VCC = 6.0 V; see Fig. 9 8
propagation delay CP to TC tpd 69 325 ns VCC = 2.0 V; see Fig. 9 8
propagation delay CP to TC tpd 25 65 ns VCC = 4.5 V; see Fig. 9 8
propagation delay CP to TC tpd 20 55 ns VCC = 6.0 V; see Fig. 9 8
propagation delay CET to TC tpd 33 225 ns VCC = 2.0 V; see Fig. 10 8
propagation delay CET to TC tpd 12 45 ns VCC = 4.5 V; see Fig. 10 8
propagation delay CET to TC tpd 10 31 ns VCC = 6.0 V; see Fig. 10 8
propagation delay MR to Qn tPHL 63 315 ns VCC = 2.0 V; see Fig. 11 8
propagation delay MR to Qn tPHL 23 63 ns VCC = 4.5 V; see Fig. 11 8
propagation delay MR to Qn tPHL 18 54 ns VCC = 6.0 V; see Fig. 11 8
pulse width CP tW 120 22 ns VCC = 2.0 V; CP HIGH or LOW; see Fig. 9 8
pulse width CP tW 24 8 ns VCC = 4.5 V; CP HIGH or LOW; see Fig. 9 8
pulse width CP tW 20 6 ns VCC = 6.0 V; CP HIGH or LOW; see Fig. 9 8
recovery time trec 150 19 ns VCC = 2.0 V; MR to CP; see Fig. 11 9
recovery time trec 30 7 ns VCC = 4.5 V; MR to CP; see Fig. 11 9
recovery time trec 26 6 ns VCC = 6.0 V; MR to CP; see Fig. 11 9
set-up time tsu 255 47 ns VCC = 2.0 V; CEP, CET to CP; see Fig. 13 9
set-up time tsu 51 17 ns VCC = 4.5 V; CEP, CET to CP; see Fig. 13 9
set-up time tsu 43 14 ns VCC = 6.0 V; CEP, CET to CP; see Fig. 13 9
maximum frequency fmax 3 13 MHz VCC = 2.0 V; CP; see Fig. 9 9
maximum frequency fmax 15 40 MHz VCC = 4.5 V; CP; see Fig. 9 9
maximum frequency fmax 18 48 MHz VCC = 6.0 V; CP; see Fig. 9 9

CAD (KiCad official)

  • Symbol: 74HC161D
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: 74hc161d-etched.step / 74hc161d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc161d.step / 74hc161d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (17 pp, sha256 b34353c771b48198, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus off (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF