component
74HC138BQ
Public Made by Adomby adom
Nexperia Logic ICs, DHVQFN-16-EP(2.5x3.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74HC138BQ
Nexperia · Logic ICs · DHVQFN-16-EP(2.5x3.5)
74HC138BQ from Nexperia, in a DHVQFN-16-EP(2.5x3.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | Address input A0 (binary weight 0) of the 3-to-8 decoder; the input voltage range is 0 V to VCC and clamp diodes are included. |
| 2 | A1 | input | Address input A1 (binary weight 1) of the 3-to-8 decoder; the input voltage range is 0 V to VCC and clamp diodes are included. |
| 3 | A2 | input | Address input A2 (binary weight 2) of the 3-to-8 decoder; the input voltage range is 0 V to VCC and clamp diodes are included. |
| 4 | E1 | input | Enable input E1, active LOW; all outputs are HIGH unless E1 and E2 are LOW and E3 is HIGH. |
| 5 | E2 | input | Enable input E2, active LOW; all outputs are HIGH unless E1 and E2 are LOW and E3 is HIGH. |
| 6 | E3 | input | Enable input E3, active HIGH; all outputs are HIGH unless E1 and E2 are LOW and E3 is HIGH. |
| 7 | Y7 | output | Active LOW mutually exclusive decoder output Y7; the output voltage range is 0 V to VCC. |
| 8 | GND | power_in | Ground pin at 0 V; all voltages are referenced to this pin. |
| 9 | Y6 | output | Active LOW mutually exclusive decoder output Y6; the output voltage range is 0 V to VCC. |
| 10 | Y5 | output | Active LOW mutually exclusive decoder output Y5; the output voltage range is 0 V to VCC. |
| 11 | Y4 | output | Active LOW mutually exclusive decoder output Y4; the output voltage range is 0 V to VCC. |
| 12 | Y3 | output | Active LOW mutually exclusive decoder output Y3; the output voltage range is 0 V to VCC. |
| 13 | Y2 | output | Active LOW mutually exclusive decoder output Y2; the output voltage range is 0 V to VCC. |
| 14 | Y1 | output | Active LOW mutually exclusive decoder output Y1; the output voltage range is 0 V to VCC. |
| 15 | Y0 | output | Active LOW mutually exclusive decoder output Y0; the output voltage range is 0 V to VCC. |
| 16 | VCC | power_in | Supply voltage; 2.0 V to 6.0 V for 74HC138 and 4.5 V to 5.5 V for 74HCT138 per the recommended operating conditions, with a maximum absolute rating of +7 V. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | DHVQFN-16-EP(2.5x3.5) |
| Category | Logic ICs |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| input clamping current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 | |
| output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 4 | |
| output current | IO | -25 | 25 | mA | VO = -0.5 V to (VCC + 0.5 V) | 4 | |
| quiescent supply current | ICC | 50 | mA | 4 | |||
| ground current | IGND | -50 | mA | 4 | |||
| storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| total power dissipation | Ptot | 500 | mW | 4 | |||
| supply voltage | VCC | 2 | 5 | 6 | V | 5 | |
| ambient temperature | Tamb | -40 | 25 | 125 | °C | 5 | |
| input transition rise and fall rate | Δt/ΔV | 625 | ns/V | VCC = 2.0 V | 5 | ||
| input transition rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC = 4.5 V | 5 | |
| input transition rise and fall rate | Δt/ΔV | 83 | ns/V | VCC = 6.0 V | 5 | ||
| HIGH-level input voltage | VIH | 1.5 | 1.2 | V | VCC = 2.0 V | 5 | |
| HIGH-level input voltage | VIH | 3.15 | 2.4 | V | VCC = 4.5 V | 5 | |
| HIGH-level input voltage | VIH | 4.2 | 3.2 | V | VCC = 6.0 V | 5 | |
| LOW-level input voltage | VIL | 0.8 | 0.5 | V | VCC = 2.0 V | 5 | |
| LOW-level input voltage | VIL | 2.1 | 1.35 | V | VCC = 4.5 V | 5 | |
| LOW-level input voltage | VIL | 2.8 | 1.8 | V | VCC = 6.0 V | 5 | |
| HIGH-level output voltage | VOH | 1.9 | 2 | V | IO = -20 μA; VCC = 2.0 V | 5 | |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | IO = -20 μA; VCC = 4.5 V | 5 | |
| HIGH-level output voltage | VOH | 5.9 | 6 | V | IO = -20 μA; VCC = 6.0 V | 5 | |
| HIGH-level output voltage | VOH | 3.98 | 4.32 | V | IO = -4.0 mA; VCC = 4.5 V | 5 | |
| HIGH-level output voltage | VOH | 5.48 | 5.81 | V | IO = -5.2 mA; VCC = 6.0 V | 5 | |
| LOW-level output voltage | VOL | 0 | 0.1 | V | IO = 20 μA; VCC = 2.0 V | 5 | |
| LOW-level output voltage | VOL | 0.15 | 0.26 | V | IO = 4.0 mA; VCC = 4.5 V | 5 | |
| LOW-level output voltage | VOL | 0.16 | 0.26 | V | IO = 5.2 mA; VCC = 6.0 V | 5 | |
| input leakage current | II | -0.1 | 0.1 | μA | VI = VCC or GND; VCC = 6.0 V | 5 | |
| supply current | ICC | 8 | μA | VI = VCC or GND; IO = 0 A; VCC = 6.0 V | 5 | ||
| input capacitance | CI | 3.5 | pF | 5 | |||
| propagation delay An to Yn | tpd | 41 | 150 | ns | An to Yn; see Fig. 4; VCC = 2.0 V | 7 | |
| propagation delay An to Yn | tpd | 15 | 30 | ns | An to Yn; see Fig. 4; VCC = 4.5 V | 7 | |
| propagation delay An to Yn | tpd | 12 | ns | An to Yn; see Fig. 4; VCC = 5 V; CL = 15 pF | 7 | ||
| propagation delay An to Yn | tpd | 12 | 26 | ns | An to Yn; see Fig. 4; VCC = 6.0 V | 7 | |
| propagation delay E3 to Yn | tpd | 47 | 150 | ns | E3 to Yn; see Fig. 4; VCC = 2.0 V | 7 | |
| propagation delay E3 to Yn | tpd | 17 | 20 | ns | E3 to Yn; see Fig. 4; VCC = 4.5 V | 7 | |
| propagation delay E3 to Yn | tpd | 14 | ns | E3 to Yn; see Fig. 4; VCC = 5 V; CL = 15 pF | 7 | ||
| propagation delay E3 to Yn | tpd | 14 | 26 | ns | E3 to Yn; see Fig. 4; VCC = 6.0 V | 7 | |
| propagation delay En to Yn | tpd | 47 | 150 | ns | En to Yn; see Fig. 5; VCC = 2.0 V | 7 | |
| propagation delay En to Yn | tpd | 17 | 20 | ns | En to Yn; see Fig. 5; VCC = 4.5 V | 7 | |
| propagation delay En to Yn | tpd | 14 | ns | En to Yn; see Fig. 5; VCC = 5 V; CL = 15 pF | 7 | ||
| propagation delay En to Yn | tpd | 14 | 26 | ns | En to Yn; see Fig. 5; VCC = 6.0 V | 7 | |
| propagation delay Yn | tpd | 19 | 75 | ns | Yn; see Fig. 4 and Fig. 5; VCC = 2.0 V | 7 | |
| propagation delay Yn | tpd | 7 | 15 | ns | Yn; see Fig. 4 and Fig. 5; VCC = 4.5 V | 7 | |
| transition time | tt | 6 | 13 | ns | Yn; see Fig. 4 and Fig. 5; VCC = 6.0 V | 7 | |
| power dissipation capacitance | CPD | 67 | pF | CL = 50 pF; f = 1 MHz; VI = GND to VCC | 7 | ||
| thermal derating of total power dissipation | Ptot | 11.2 | mW/K | SOT763-1 (DHVQFN16); derates linearly above 106 °C | 4 |
CAD (KiCad official)
- Symbol:
74HC138BQ - Footprint:
Package_DFN_QFN:DHVQFN-16-1EP_2.5x3.5mm_P0.5mm_EP1x2mm - 3D model: DHVQFN-16-EP(2.5x3.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
74hc138bq-etched.step/74hc138bq-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc138bq.step/74hc138bq.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (15 pp, sha256
645120bc441507e9, retrieved 2026-10-17, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).