component
74HC112PW
Public Made by Adomby adom
Nexperia Flip Flops, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74HC112PW
Nexperia · Flip Flops · TSSOP-16
74HC112PW from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1CP | input | Clock input of flip-flop 1, negative-edge triggered on the HIGH-to-LOW transition, with Schmitt-trigger action tolerant of slow clock rise and fall times. |
| 2 | 1K | input | Data input K of flip-flop 1, which must be stable one set-up time before the HIGH-to-LOW clock transition. |
| 3 | 1J | input | Data input J of flip-flop 1, which must be stable one set-up time before the HIGH-to-LOW clock transition. |
| 4 | 1SD | input | Asynchronous set input of flip-flop 1, active LOW, operating independently of the clock. |
| 5 | 1Q | output | True flip-flop output of flip-flop 1. |
| 6 | 1Q | output | Complement flip-flop output of flip-flop 1. |
| 7 | 2Q | output | Complement flip-flop output of flip-flop 2. |
| 8 | GND | power_in | Ground reference at 0 V for all voltages in the datasheet. |
| 9 | 2Q | output | True flip-flop output of flip-flop 2. |
| 10 | 2SD | input | Asynchronous set input of flip-flop 2, active LOW, operating independently of the clock. |
| 11 | 2J | input | Data input J of flip-flop 2, which must be stable one set-up time before the HIGH-to-LOW clock transition. |
| 12 | 2K | input | Data input K of flip-flop 2, which must be stable one set-up time before the HIGH-to-LOW clock transition. |
| 13 | 2CP | input | Clock input of flip-flop 2, negative-edge triggered on the HIGH-to-LOW transition. |
| 14 | 2RD | input | Asynchronous reset input of flip-flop 2, active LOW, operating independently of the clock. |
| 15 | 1RD | input | Asynchronous reset input of flip-flop 1, active LOW, operating independently of the clock. |
| 16 | VCC | power_in | Supply voltage; recommended 2.0 V to 6.0 V for 74HC112 and 4.5 V to 5.5 V for 74HCT112, with absolute maximum -0.5 V to +7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| Input clamping current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 | |
| Output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 4 | |
| Output current | IO | -25 | 25 | mA | -0.5 V < VO < VCC + 0.5 V | 4 | |
| Supply current | ICC | 50 | mA | 4 | |||
| Ground current | IGND | -50 | mA | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Total power dissipation | Ptot | 500 | mW | SOT403-1 (TSSOP16): derates linearly with 8.5 mW/K above 91 °C | 4 | ||
| Supply voltage | VCC | 2 | 5 | 6 | V | 74HC112 | 4 |
| Input voltage | VI | 0 | V | maximum VCC | 4 | ||
| Output voltage | VO | 0 | V | maximum VCC | 4 | ||
| Ambient temperature | Tamb | -40 | 25 | 125 | °C | 4 | |
| Input transition rise and fall rate | Δt/ΔV | 625 | ns/V | VCC = 2.0 V | 4 | ||
| Input transition rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC = 4.5 V | 4 | |
| Input transition rise and fall rate | Δt/ΔV | 83 | ns/V | VCC = 6.0 V | 4 | ||
| HIGH-level input voltage | VIH | 1.5 | 1.2 | V | VCC = 2.0 V; -40 °C to +125 °C | 4 | |
| HIGH-level input voltage | VIH | 3.15 | 2.4 | V | VCC = 4.5 V; -40 °C to +125 °C | 4 | |
| HIGH-level input voltage | VIH | 4.2 | 3.2 | V | VCC = 6.0 V; -40 °C to +125 °C | 4 | |
| LOW-level input voltage | VIL | 0.8 | 0.5 | V | VCC = 2.0 V; -40 °C to +125 °C | 4 | |
| LOW-level input voltage | VIL | 2.1 | 1.35 | V | VCC = 4.5 V; -40 °C to +125 °C | 4 | |
| LOW-level input voltage | VIL | 2.8 | 1.8 | V | VCC = 6.0 V; -40 °C to +125 °C | 4 | |
| HIGH-level output voltage | VOH | 1.9 | 2 | V | VI = VIH or VIL; IO = -20 μA; VCC = 2.0 V; -40 °C to +125 °C | 5 | |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V; -40 °C to +125 °C | 5 | |
| HIGH-level output voltage | VOH | 5.9 | 6 | V | VI = VIH or VIL; IO = -20 μA; VCC = 6.0 V; -40 °C to +125 °C | 5 | |
| HIGH-level output voltage | VOH | 3.7 | 4.32 | V | VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V; -40 °C to +125 °C | 5 | |
| HIGH-level output voltage | VOH | 5.2 | 5.81 | V | VI = VIH or VIL; IO = -5.2 mA; VCC = 6.0 V; -40 °C to +125 °C | 5 | |
| LOW-level output voltage | VOL | 0 | 0.1 | V | VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V; -40 °C to +125 °C | 5 | |
| LOW-level output voltage | VOL | 0.15 | 0.4 | V | VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V; -40 °C to +125 °C | 5 | |
| LOW-level output voltage | VOL | 0.16 | 0.4 | V | VI = VIH or VIL; IO = 5.2 mA; VCC = 6.0 V; -40 °C to +125 °C | 5 | |
| Input leakage current | II | -1 | 1 | μA | VI = VCC or GND; VCC = 6.0 V; -40 °C to +125 °C | 5 | |
| Supply current | ICC | 80 | μA | VI = VCC or GND; IO = 0 A; VCC = 6.0 V; -40 °C to +125 °C | 5 | ||
| Propagation delay nCP to nQ | tpd | 55 | 265 | ns | see Fig. 4; VCC = 2.0 V; -40 °C to +125 °C | 6 | |
| Propagation delay nCP to nQ | tpd | 20 | 53 | ns | see Fig. 4; VCC = 4.5 V; -40 °C to +125 °C | 6 | |
| Propagation delay nCP to nQ | tpd | 16 | 45 | ns | see Fig. 4; VCC = 6.0 V; -40 °C to +125 °C | 6 | |
| Propagation delay nRD to nQ, nQ | tpd | 58 | 270 | ns | see Fig. 5; VCC = 2.0 V; -40 °C to +125 °C | 6 | |
| Propagation delay nRD to nQ, nQ | tpd | 21 | 54 | ns | see Fig. 5; VCC = 4.5 V; -40 °C to +125 °C | 6 | |
| Propagation delay nRD to nQ, nQ | tpd | 17 | 46 | ns | see Fig. 5; VCC = 6.0 V; -40 °C to +125 °C | 6 | |
| Propagation delay nSD to nQ, nQ | tpd | 50 | 235 | ns | see Fig. 5; VCC = 2.0 V; -40 °C to +125 °C | 6 | |
| Propagation delay nSD to nQ, nQ | tpd | 18 | 47 | ns | see Fig. 5; VCC = 4.5 V; -40 °C to +125 °C | 6 | |
| Propagation delay nSD to nQ, nQ | tpd | 14 | 40 | ns | see Fig. 5; VCC = 6.0 V; -40 °C to +125 °C | 6 | |
| Pulse width nSD, nRD LOW | tW | 120 | 22 | ns | see Fig. 5; VCC = 2.0 V; -40 °C to +125 °C | 6 | |
| Pulse width nSD, nRD LOW | tW | 24 | 8 | ns | see Fig. 5; VCC = 4.5 V; -40 °C to +125 °C | 6 | |
| Pulse width nSD, nRD LOW | tW | 20 | 6 | ns | see Fig. 5; VCC = 6.0 V; -40 °C to +125 °C | 6 | |
| Recovery time nRD to nCP | trec | 150 | 22 | ns | see Fig. 5; VCC = 2.0 V; -40 °C to +125 °C | 7 | |
| Recovery time nRD to nCP | trec | 30 | 8 | ns | see Fig. 5; VCC = 4.5 V; -40 °C to +125 °C | 7 | |
| Recovery time nRD to nCP | trec | 26 | 6 | ns | see Fig. 5; VCC = 6.0 V; -40 °C to +125 °C | 7 | |
| Recovery time nSD to nCP | trec | 120 | -19 | ns | see Fig. 5; VCC = 2.0 V; -40 °C to +125 °C | 7 | |
| Recovery time nSD to nCP | trec | 24 | -7 | ns | see Fig. 5; VCC = 4.5 V; -40 °C to +125 °C | 7 | |
| Recovery time nSD to nCP | trec | 20 | -6 | ns | see Fig. 5; VCC = 6.0 V; -40 °C to +125 °C | 7 | |
| Set-up time nJ and nK to nCP | tsu | 120 | 19 | ns | see Fig. 4; VCC = 2.0 V; -40 °C to +125 °C | 7 | |
| Set-up time nJ and nK to nCP | tsu | 24 | 7 | ns | see Fig. 4; VCC = 4.5 V; -40 °C to +125 °C | 7 | |
| Set-up time nJ and nK to nCP | tsu | 20 | 6 | ns | see Fig. 4; VCC = 6.0 V; -40 °C to +125 °C | 7 | |
| Hold time nJ and nK to nCP | th | 0 | -11 | ns | see Fig. 4; VCC = 2.0 V; -40 °C to +125 °C | 7 | |
| Hold time nJ and nK to nCP | th | 0 | -4 | ns | see Fig. 4; VCC = 4.5 V; -40 °C to +125 °C | 7 | |
| Hold time nJ and nK to nCP | th | 0 | -3 | ns | see Fig. 4; VCC = 6.0 V; -40 °C to +125 °C | 7 | |
| Maximum frequency nCP | fmax | 4 | 20 | MHz | see Fig. 4; VCC = 2.0 V; -40 °C to +125 °C | 7 | |
| Maximum frequency nCP | fmax | 20 | 60 | MHz | see Fig. 4; VCC = 4.5 V; -40 °C to +125 °C | 7 | |
| Maximum frequency nCP | fmax | 24 | 71 | MHz | see Fig. 4; VCC = 6.0 V; -40 °C to +125 °C | 7 |
CAD (KiCad official)
- Symbol:
74HC112PW - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
74hc112pw-etched.step/74hc112pw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc112pw.step/74hc112pw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (16 pp, sha256
2882cca3283b6ef0, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).