component
74HC08S
Public Made by Adomby adom
GR Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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74HC08S
GR · Logic Gates · SOP-14
74HC08S from GR, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A1 | input | Input A of 2-input AND gate 1, with input current limited to 1 µA maximum and input voltage kept between -0.3 V and VCC+0.3 V. |
| 2 | B1 | input | Input B of 2-input AND gate 1, with input current limited to 1 µA maximum and input voltage kept between -0.3 V and VCC+0.3 V. |
| 3 | Y1 | output | Push-pull buffered output of AND gate 1, with output current limited to 25 mA maximum per pin. |
| 4 | A2 | input | Input A of 2-input AND gate 2, with input current limited to 1 µA maximum and input voltage kept between -0.3 V and VCC+0.3 V. |
| 5 | B2 | input | Input B of 2-input AND gate 2, with input current limited to 1 µA maximum and input voltage kept between -0.3 V and VCC+0.3 V. |
| 6 | Y2 | output | Push-pull buffered output of AND gate 2, with output current limited to 25 mA maximum per pin. |
| 7 | GND | power_in | Ground reference pin for the device. |
| 8 | Y3 | output | Push-pull buffered output of AND gate 3, with output current limited to 25 mA maximum per pin. |
| 9 | A3 | input | Input A of 2-input AND gate 3, with input current limited to 1 µA maximum and input voltage kept between -0.3 V and VCC+0.3 V. |
| 10 | B3 | input | Input B of 2-input AND gate 3, with input current limited to 1 µA maximum and input voltage kept between -0.3 V and VCC+0.3 V. |
| 11 | Y4 | output | Push-pull buffered output of AND gate 4, with output current limited to 25 mA maximum per pin. |
| 12 | A4 | input | Input A of 2-input AND gate 4, with input current limited to 1 µA maximum and input voltage kept between -0.3 V and VCC+0.3 V. |
| 13 | B4 | input | Input B of 2-input AND gate 4, with input current limited to 1 µA maximum and input voltage kept between -0.3 V and VCC+0.3 V. |
| 14 | VCC | power_in | Positive supply pin; operating range is 2.0 V to 6.0 V, with an absolute maximum of 6.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GR |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating voltage (absolute maximum) | VCC | 6.5 | V | 1 | |||
| Single pin output current | IOUT | 25 | mA | 1 | |||
| VCC or GND current | ICC | 50 | mA | 1 | |||
| Power dissipation | PD | 500 | mW | 1 | |||
| Operating temperature | TA | 0 | 70 | ℃ | 1 | ||
| Storage temperature | TS | -65 | 150 | ℃ | 1 | ||
| Lead soldering temperature | TW | 260 | ℃ | 10s | 1 | ||
| Input/output voltage | VIN, VOUT | -0.3 | V | 1 | |||
| Operating voltage | VCC | 2 | 5 | 6 | V | 2 | |
| Input/output voltage | VIN, VOUT | 0 | V | 2 | |||
| Input rise/fall time | Tr, tf | 0 | 1000 | ns | VCC=2.0V | 2 | |
| Input rise/fall time | Tr, tf | 0 | 500 | ns | VCC=4.5V | 2 | |
| Input rise/fall time | Tr, tf | 0 | 400 | ns | VCC=6.0V | 2 | |
| Operating temperature | TA | 0 | 60 | ℃ | 2 | ||
| High-level input voltage | VIH | 1.5 | V | TA=25℃, VCC=2.0V | 2 | ||
| High-level input voltage | VIH | 3.15 | V | TA=25℃, VCC=4.5V | 2 | ||
| High-level input voltage | VIH | 4.2 | V | TA=25℃, VCC=6.0V | 2 | ||
| Low-level input voltage | VIL | 0.5 | V | TA=25℃, VCC=2.0V | 2 | ||
| Low-level input voltage | VIL | 1.35 | V | TA=25℃, VCC=4.5V | 2 | ||
| Low-level input voltage | VIL | 1.8 | V | TA=25℃, VCC=6.0V | 2 | ||
| High-level output voltage | VOH | 1.9 | V | TA=25℃, VI=VIH or VIL, /IOUT/≤20μA, VCC=2.0V | 2 | ||
| High-level output voltage | VOH | 4.4 | V | TA=25℃, VI=VIH or VIL, /IOUT/≤20μA, VCC=4.5V | 2 | ||
| High-level output voltage | VOH | 5.9 | V | TA=25℃, VI=VIH or VIL, /IOUT/≤20μA, VCC=6.0V | 2 | ||
| High-level output voltage | VOH | 3.7 | 4.4 | V | TA=25℃, VI=VIH, VIL, /IOUT/≤4.0mA, VCC=4.5V | 2 | |
| High-level output voltage | VOH | 5.2 | 5.8 | V | TA=25℃, VI=VIH, VIL, /IOUT/≤5.2mA, VCC=6.0V | 2 | |
| Low-level output voltage | VOL | 0.1 | V | TA=25℃, VI=VIH or VIL, /IOUT/≤20μA, VCC=2.0V | 2 | ||
| Low-level output voltage | VOL | 0.06 | 0.4 | V | TA=25℃, VI=VIH, VIL, /IOUT/≤4.0mA, VCC=4.5V | 2 | |
| Low-level output voltage | VOL | 0.07 | 0.4 | V | TA=25℃, VI=VIH, VIL, /IOUT/≤5.2mA, VCC=6.0V | 2 | |
| Input current | IIN | 1 | uA | TA=25℃, VI=VCC or GND, VCC=6.0V | 2 | ||
| Operating current | ICC | 5.5 | uA | TA=25℃, VI=VCC or GND, IOUT=0μA, VCC=6.0V | 2 | ||
| Maximum propagation delay time A, B to Y | tPHL | 16 | ns | TA=25℃, VCC=5.0V, tr=tf≤20ns, CL=15pF | 3 | ||
| Maximum propagation delay time A, B to Y | tPLH | 18 | ns | TA=25℃, VCC=5.0V, tr=tf≤20ns, CL=15pF | 3 |
CAD (KiCad official)
- Symbol:
74HC08S - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files:
74hc08s-etched.step/74hc08s-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc08s.step/74hc08s.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: GR datasheet (5 pp, sha256
6b1d9c68d902a705, retrieved 2026-10-21, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).