component
74HC08N
Public Made by Adomby adom
HGSEMI Logic Gates, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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|---|---|
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| 74hc08n-etched.step | 8d ago |
| 74hc08n-hero.glb | 8d ago |
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74HC08N
HGSEMI · Logic Gates · DIP-14
74HC08N from HGSEMI, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input 1A of gate 1; inputs must stay between GND and VCC (recommended VCC 2.0 V to 6.0 V). |
| 2 | 1B | input | Data input 1B of gate 1; inputs must stay between GND and VCC (recommended VCC 2.0 V to 6.0 V). |
| 3 | 1Y | output | Data output 1Y of gate 1, logic function Y = A AND B. |
| 4 | 2A | input | Data input 2A of gate 2; inputs must stay between GND and VCC (recommended VCC 2.0 V to 6.0 V). |
| 5 | 2B | input | Data input 2B of gate 2; inputs must stay between GND and VCC (recommended VCC 2.0 V to 6.0 V). |
| 6 | 2Y | output | Output 2Y of gate 2, logic function Y = A AND B; the datasheet labels this pin 输入输出 (input/output), which is treated here as the gate output per the truth table. |
| 7 | GND | power_in | Ground reference (0 V) for the device. |
| 8 | 3Y | output | Data output 3Y of gate 3, logic function Y = A AND B. |
| 9 | 3A | input | Data input 3A of gate 3; inputs must stay between GND and VCC (recommended VCC 2.0 V to 6.0 V). |
| 10 | 3B | input | Data input 3B of gate 3; inputs must stay between GND and VCC (recommended VCC 2.0 V to 6.0 V). |
| 11 | 4Y | output | Data output 4Y of gate 4, logic function Y = A AND B. |
| 12 | 4A | input | Data input 4A of gate 4; inputs must stay between GND and VCC (recommended VCC 2.0 V to 6.0 V). |
| 13 | 4B | input | Data input 4B of gate 4; inputs must stay between GND and VCC (recommended VCC 2.0 V to 6.0 V). |
| 14 | VCC | power_in | Supply voltage; recommended range 2.0 V to 6.0 V, absolute maximum +7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HGSEMI |
| Package | DIP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 2 | ||
| Input clamp current | IIK | -20 | 20 | mA | VO<-0.5V or VO>VCC+0.5V | 2 | |
| Output clamp current | IOK | -20 | 20 | mA | VO=-0.5V~VCC+0.5V | 2 | |
| Output current | IO | -25 | 25 | mA | 2 | ||
| VCC or GND current | ICC,IGND | -50 | 50 | mA | 2 | ||
| Storage temperature | TSTG | -65 | 150 | ℃ | 2 | ||
| Supply voltage | VCC | 2 | 5 | 6 | V | 3 | |
| Input voltage | VI | 0 | V | 3 | |||
| Input rise and fall time | tr,tf | 1000 | ns | VCC=2.0V | 3 | ||
| Input rise and fall time | tr,tf | 6 | 500 | ns | VCC=4.5V | 3 | |
| Input rise and fall time | tr,tf | 400 | ns | VCC=6.0V | 3 | ||
| Operating temperature | Tamb | -40 | 25 | 85 | ℃ | 3 | |
| High-level input voltage | VIH | 1.5 | 1.2 | V | VCC=2.0V | 3 | |
| High-level input voltage | VIH | 3.15 | 2.4 | V | VCC=4.5V | 3 | |
| High-level input voltage | VIH | 4.2 | 3.2 | V | VCC=6.0V | 3 | |
| Low-level input voltage | VIL | 0.8 | 0.5 | V | VCC=2.0V | 3 | |
| Low-level input voltage | VIL | 2.1 | 1.35 | V | VCC=4.5V | 3 | |
| Low-level input voltage | VIL | 2.8 | 1.8 | V | VCC=6.0V | 3 | |
| High-level output voltage | VOH | 1.9 | 2 | V | Vi=VIH或VIL, VCC=2.0V, IO=-20uA | 3 | |
| High-level output voltage | VOH | 4.4 | 4.5 | V | Vi=VIH或VIL, VCC=4.5V, IO=-20uA | 3 | |
| High-level output voltage | VOH | 5.9 | 6 | V | Vi=VIH或VIL, VCC=6.0V, IO=-20uA | 3 | |
| High-level output voltage | VOH | 3.98 | 4.32 | V | Vi=VIH或VIL, VCC=4.5V, IO=-4.0mA | 3 | |
| High-level output voltage | VOH | 5.48 | 5.81 | V | Vi=VIH或VIL, VCC=6.0V, IO=-5.2mA | 3 | |
| Low-level output voltage | VOL | 0 | 0.1 | V | Vi=VIH或VIL, VCC=2.0V, IO=20uA | 3 | |
| Low-level output voltage | VOL | 0.15 | 0.26 | V | Vi=VIH或VIL, VCC=4.5V, IO=4.0mA | 3 | |
| Low-level output voltage | VOL | 0.16 | 0.26 | V | Vi=VIH或VIL, VCC=6.0V, IO=5.2mA | 3 | |
| Input leakage current | ILI | -0.1 | 0.1 | uA | Vi=VCC或GND, VCC=6.0V | 3 | |
| Quiescent supply current | ICC | 2 | uA | Vi=VCC或GND, VCC=6.0V, IO=0 | 3 | ||
| High-level input voltage (-40 to 85 ℃) | VIH | 1.5 | V | VCC=2.0V | 4 | ||
| High-level input voltage (-40 to 85 ℃) | VIH | 3.15 | V | VCC=4.5V | 4 | ||
| High-level input voltage (-40 to 85 ℃) | VIH | 4.2 | V | VCC=6.0V | 4 | ||
| Low-level input voltage (-40 to 85 ℃) | VIL | 0.5 | V | VCC=2.0V | 4 | ||
| Low-level input voltage (-40 to 85 ℃) | VIL | 1.35 | V | VCC=4.5V | 4 | ||
| Low-level input voltage (-40 to 85 ℃) | VIL | 1.8 | V | VCC=6.0V | 4 | ||
| High-level output voltage (-40 to 85 ℃) | VOH | 1.9 | V | Vi=VIH或VIL, VCC=2.0V, IO=-20uA | 4 | ||
| High-level output voltage (-40 to 85 ℃) | VOH | 4.4 | V | Vi=VIH或VIL, VCC=4.5V, IO=-20uA | 4 | ||
| High-level output voltage (-40 to 85 ℃) | VOH | 5.9 | V | Vi=VIH或VIL, VCC=6.0V, IO=-20uA | 4 | ||
| High-level output voltage (-40 to 85 ℃) | VOH | 3.84 | V | Vi=VIH或VIL, VCC=4.5V, IO=-4.0mA | 4 | ||
| High-level output voltage (-40 to 85 ℃) | VOH | 5.34 | V | Vi=VIH或VIL, VCC=6.0V, IO=-5.2mA | 4 | ||
| Low-level output voltage (-40 to 85 ℃) | VOL | 0.1 | V | Vi=VIH或VIL, VCC=2.0V, IO=20uA | 4 | ||
| Low-level output voltage (-40 to 85 ℃) | VOL | 0.33 | V | Vi=VIH或VIL, VCC=4.5V, IO=4.0mA | 4 | ||
| Input leakage current (-40 to 85 ℃) | ILI | -1 | 1 | uA | Vi=VCC或GND, VCC=6.0V | 4 | |
| Quiescent supply current (-40 to 85 ℃) | ICC | 20 | uA | Vi=VCC或GND, VCC=6.0V, IO=0 | 4 | ||
| nA,nB to nY propagation delay | tPHL/tPLH | 25 | 90 | ns | VCC=2.0V | 4 | |
| nA,nB to nY propagation delay | tPHL/tPLH | 9 | 18 | ns | VCC=4.5V | 4 | |
| nA,nB to nY propagation delay | tPHL/tPLH | 7 | 15 | ns | VCC=6.0V | 4 | |
| Output transition time | tTHL/tTLH | 19 | 75 | ns | VCC=2.0V | 4 | |
| Output transition time | tTHL/tTLH | 7 | 15 | ns | VCC=4.5V | 4 | |
| Output transition time | tTHL/tTLH | 6 | 13 | ns | VCC=6.0V | 4 |
CAD (KiCad official)
- Symbol:
74HC08N - Footprint:
Package_DIP:DIP-14_W7.62mm - 3D model: DIP-14 (KiCad packages3D, STEP)
- 3D model files:
74hc08n-etched.step/74hc08n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc08n.step/74hc08n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HGSEMI datasheet (8 pp, sha256
30597e2a281acfcd, retrieved 2026-10-14, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).