component
74HC08BQ-Q100
Public Made by Adomby adom
Nexperia Logic Gates, DHVQFN-14-EP(2.5x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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74HC08BQ-Q100
Nexperia · Logic Gates · DHVQFN-14-EP(2.5x3)
74HC08BQ-Q100 from Nexperia, in a DHVQFN-14-EP(2.5x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input 1A of AND gate 1; input voltage range is 0 V to VCC and the input includes a clamp diode, allowing current-limiting resistors for voltages above VCC. |
| 2 | 1B | input | Data input 1B of AND gate 1; input voltage range is 0 V to VCC and the input includes a clamp diode, allowing current-limiting resistors for voltages above VCC. |
| 3 | 1Y | output | Data output 1Y of AND gate 1; output voltage range is 0 V to VCC. |
| 4 | 2A | input | Data input 2A of AND gate 2; input voltage range is 0 V to VCC and the input includes a clamp diode, allowing current-limiting resistors for voltages above VCC. |
| 5 | 2B | input | Data input 2B of AND gate 2; input voltage range is 0 V to VCC and the input includes a clamp diode, allowing current-limiting resistors for voltages above VCC. |
| 6 | 2Y | output | Data output 2Y of AND gate 2; output voltage range is 0 V to VCC. |
| 7 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 8 | 3Y | output | Data output 3Y of AND gate 3; output voltage range is 0 V to VCC. |
| 9 | 3A | input | Data input 3A of AND gate 3; input voltage range is 0 V to VCC and the input includes a clamp diode, allowing current-limiting resistors for voltages above VCC. |
| 10 | 3B | input | Data input 3B of AND gate 3; input voltage range is 0 V to VCC and the input includes a clamp diode, allowing current-limiting resistors for voltages above VCC. |
| 11 | 4Y | output | Data output 4Y of AND gate 4; output voltage range is 0 V to VCC. |
| 12 | 4A | input | Data input 4A of AND gate 4; input voltage range is 0 V to VCC and the input includes a clamp diode, allowing current-limiting resistors for voltages above VCC. |
| 13 | 4B | input | Data input 4B of AND gate 4; input voltage range is 0 V to VCC and the input includes a clamp diode, allowing current-limiting resistors for voltages above VCC. |
| 14 | VCC | power_in | Supply voltage; 2.0 V to 6.0 V for 74HC08-Q100 and 4.5 V to 5.5 V for 74HCT08-Q100 per recommended operating conditions, absolute maximum -0.5 V to +7 V. |
| 15 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | DHVQFN-14-EP(2.5x3) |
| Category | Logic |
| Pins | 15 |
CAD (KiCad official)
- Symbol:
74HC08BQ-Q100 - Footprint:
Package_DFN_QFN:DHVQFN-14-1EP_2.5x3mm_P0.5mm_EP1x1.5mm - 3D model: DHVQFN-14-EP(2.5x3), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
74hc08bq-q100-etched.step/74hc08bq-q100-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc08bq-q100.step/74hc08bq-q100.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (13 pp, sha256
6f32abaec1b6f0ca, retrieved 2026-10-09, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).