component
74HC05D
Public Made by Adomby adom
Nexperia Inverters, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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74HC05D
Nexperia · Inverters · SOIC-14
74HC05D from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input of inverter 1, with CMOS input levels; input voltage is limited to 0 V to VCC. |
| 2 | 1Y | output | Open-drain output of inverter 1, which goes LOW when 1A is HIGH and is high-impedance when 1A is LOW; it requires an external pull-up resistor. |
| 3 | 2A | input | Data input of inverter 2, with CMOS input levels; input voltage is limited to 0 V to VCC. |
| 4 | 2Y | output | Open-drain output of inverter 2, which goes LOW when 2A is HIGH and is high-impedance when 2A is LOW; it requires an external pull-up resistor. |
| 5 | 3A | input | Data input of inverter 3, with CMOS input levels; input voltage is limited to 0 V to VCC. |
| 6 | 3Y | output | Open-drain output of inverter 3, which goes LOW when 3A is HIGH and is high-impedance when 3A is LOW; it requires an external pull-up resistor. |
| 7 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 8 | 4Y | output | Open-drain output of inverter 4, which goes LOW when 4A is HIGH and is high-impedance when 4A is LOW; it requires an external pull-up resistor. |
| 9 | 4A | input | Data input of inverter 4, with CMOS input levels; input voltage is limited to 0 V to VCC. |
| 10 | 5Y | output | Open-drain output of inverter 5, which goes LOW when 5A is HIGH and is high-impedance when 5A is LOW; it requires an external pull-up resistor. |
| 11 | 5A | input | Data input of inverter 5, with CMOS input levels; input voltage is limited to 0 V to VCC. |
| 12 | 6Y | output | Open-drain output of inverter 6, which goes LOW when 6A is HIGH and is high-impedance when 6A is LOW; it requires an external pull-up resistor. |
| 13 | 6A | input | Data input of inverter 6, with CMOS input levels; input voltage is limited to 0 V to VCC. |
| 14 | VCC | power_in | Supply voltage; recommended operating range is 2.0 V to 6.0 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| input clamping current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V [1] | 4 | |
| output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V [1] | 4 | |
| output voltage | VO | -0.5 | V | [1]; maximum printed as VCC + 0.5 V | 4 | ||
| output current | IO | 25 | mA | VO < VCC + 0.5 V | 4 | ||
| supply current | ICC | 50 | mA | 4 | |||
| ground current | IGND | -50 | mA | 4 | |||
| storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| total power dissipation | Ptot | 500 | mW | [2] SOT108-1 (SO14); derates linearly 10.1 mW/K above 100 °C | 4 | ||
| supply voltage | VCC | 2 | 5 | 6 | V | 4 | |
| input voltage | VI | 0 | V | maximum printed as VCC | 4 | ||
| output voltage | VO | 0 | V | maximum printed as VCC | 4 | ||
| ambient temperature | Tamb | -40 | 125 | °C | 4 | ||
| input transition rise and fall rate | Δt/ΔV | 625 | ns/V | VCC = 2.0 V | 4 | ||
| input transition rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC = 4.5 V | 4 | |
| input transition rise and fall rate | Δt/ΔV | 83 | ns/V | VCC = 6.0 V | 4 | ||
| HIGH-level input voltage | VIH | 1.5 | 1.2 | V | VCC = 2.0 V; -40 °C to +125 °C; typ at 25 °C | 5 | |
| HIGH-level input voltage | VIH | 3.15 | 2.4 | V | VCC = 4.5 V; -40 °C to +125 °C; typ at 25 °C | 5 | |
| HIGH-level input voltage | VIH | 4.2 | 3.2 | V | VCC = 6.0 V; -40 °C to +125 °C; typ at 25 °C | 5 | |
| LOW-level input voltage | VIL | 0.8 | 0.5 | V | VCC = 2.0 V; -40 °C to +125 °C; typ at 25 °C | 5 | |
| LOW-level input voltage | VIL | 2.1 | 1.35 | V | VCC = 4.5 V; -40 °C to +125 °C; typ at 25 °C | 5 | |
| LOW-level input voltage | VIL | 2.8 | 1.8 | V | VCC = 6.0 V; -40 °C to +125 °C; typ at 25 °C | 5 | |
| LOW-level output voltage | VOL | 0 | 0.1 | V | VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V; -40 °C to +125 °C | 5 | |
| LOW-level output voltage | VOL | 0.15 | 0.4 | V | VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V; -40 °C to +125 °C | 5 | |
| LOW-level output voltage | VOL | 0.16 | 0.4 | V | VI = VIH or VIL; IO = 5.2 mA; VCC = 6.0 V; -40 °C to +125 °C | 5 | |
| input leakage current | II | -1 | 1 | μA | VI = VCC or GND; VCC = 6.0 V; -40 °C to +125 °C | 5 | |
| OFF-state output current | IOZ | -10 | 10 | μA | VI = VIL; VO = VCC or GND; VCC = 6.0 V; -40 °C to +125 °C | 5 | |
| supply current | ICC | 40 | μA | VI = VCC or GND; IO = 0 A; VCC = 6.0 V; -40 °C to +125 °C | 5 | ||
| LOW to OFF-state propagation delay | tPLZ | 20 | 135 | ns | nA to nY; see Fig. 6; VCC = 2.0 V; -40 °C to +125 °C | 6 | |
| LOW to OFF-state propagation delay | tPLZ | 11 | 27 | ns | nA to nY; see Fig. 6; VCC = 4.5 V; -40 °C to +125 °C | 6 | |
| LOW to OFF-state propagation delay | tPLZ | 10 | 23 | ns | nA to nY; see Fig. 6; VCC = 6.0 V; -40 °C to +125 °C | 6 | |
| OFF-state to LOW propagation delay | tPZL | 22 | 135 | ns | nA to nY; see Fig. 6; VCC = 2.0 V; -40 °C to +125 °C | 6 | |
| OFF-state to LOW propagation delay | tPZL | 9 | 27 | ns | nA to nY; see Fig. 6; VCC = 4.5 V; -40 °C to +125 °C | 6 | |
| OFF-state to LOW propagation delay | tPZL | 8 | 23 | ns | nA to nY; see Fig. 6; VCC = 6.0 V; -40 °C to +125 °C | 6 | |
| HIGH to LOW output transition time | tTHL | 18 | 110 | ns | see Fig. 6; VCC = 2.0 V; -40 °C to +125 °C | 6 | |
| HIGH to LOW output transition time | tTHL | 6 | 22 | ns | see Fig. 6; VCC = 4.5 V; -40 °C to +125 °C | 6 | |
| HIGH to LOW output transition time | tTHL | 5 | 19 | ns | see Fig. 6; VCC = 6.0 V; -40 °C to +125 °C | 6 |
CAD (KiCad official)
- Symbol:
74HC05D - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
74hc05d-etched.step/74hc05d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc05d.step/74hc05d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (13 pp, sha256
8d6999747a1b3451, retrieved 2026-10-15, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 74HC05D
**Nexperia** · Inverters · SOIC-14
74HC05D from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input of inverter 1, with CMOS input levels; input voltage is limited to 0 V to VCC. |
| 2 | 1Y | output | Open-drain output of inverter 1, which goes LOW when 1A is HIGH and is high-impedance when 1A is LOW; it requires an external pull-up resistor. |
| 3 | 2A | input | Data input of inverter 2, with CMOS input levels; input voltage is limited to 0 V to VCC. |
| 4 | 2Y | output | Open-drain output of inverter 2, which goes LOW when 2A is HIGH and is high-impedance when 2A is LOW; it requires an external pull-up resistor. |
| 5 | 3A | input | Data input of inverter 3, with CMOS input levels; input voltage is limited to 0 V to VCC. |
| 6 | 3Y | output | Open-drain output of inverter 3, which goes LOW when 3A is HIGH and is high-impedance when 3A is LOW; it requires an external pull-up resistor. |
| 7 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 8 | 4Y | output | Open-drain output of inverter 4, which goes LOW when 4A is HIGH and is high-impedance when 4A is LOW; it requires an external pull-up resistor. |
| 9 | 4A | input | Data input of inverter 4, with CMOS input levels; input voltage is limited to 0 V to VCC. |
| 10 | 5Y | output | Open-drain output of inverter 5, which goes LOW when 5A is HIGH and is high-impedance when 5A is LOW; it requires an external pull-up resistor. |
| 11 | 5A | input | Data input of inverter 5, with CMOS input levels; input voltage is limited to 0 V to VCC. |
| 12 | 6Y | output | Open-drain output of inverter 6, which goes LOW when 6A is HIGH and is high-impedance when 6A is LOW; it requires an external pull-up resistor. |
| 13 | 6A | input | Data input of inverter 6, with CMOS input levels; input voltage is limited to 0 V to VCC. |
| 14 | VCC | power_in | Supply voltage; recommended operating range is 2.0 V to 6.0 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | -0.5 | | 7 | V | | 4 |
| input clamping current | IIK | -20 | | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V [1] | 4 |
| output clamping current | IOK | -20 | | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V [1] | 4 |
| output voltage | VO | -0.5 | | | V | [1]; maximum printed as VCC + 0.5 V | 4 |
| output current | IO | | | 25 | mA | VO < VCC + 0.5 V | 4 |
| supply current | ICC | | | 50 | mA | | 4 |
| ground current | IGND | -50 | | | mA | | 4 |
| storage temperature | Tstg | -65 | | 150 | °C | | 4 |
| total power dissipation | Ptot | | | 500 | mW | [2] SOT108-1 (SO14); derates linearly 10.1 mW/K above 100 °C | 4 |
| supply voltage | VCC | 2 | 5 | 6 | V | | 4 |
| input voltage | VI | 0 | | | V | maximum printed as VCC | 4 |
| output voltage | VO | 0 | | | V | maximum printed as VCC | 4 |
| ambient temperature | Tamb | -40 | | 125 | °C | | 4 |
| input transition rise and fall rate | Δt/ΔV | | | 625 | ns/V | VCC = 2.0 V | 4 |
| input transition rise and fall rate | Δt/ΔV | | 1.67 | 139 | ns/V | VCC = 4.5 V | 4 |
| input transition rise and fall rate | Δt/ΔV | | | 83 | ns/V | VCC = 6.0 V | 4 |
| HIGH-level input voltage | VIH | 1.5 | 1.2 | | V | VCC = 2.0 V; -40 °C to +125 °C; typ at 25 °C | 5 |
| HIGH-level input voltage | VIH | 3.15 | 2.4 | | V | VCC = 4.5 V; -40 °C to +125 °C; typ at 25 °C | 5 |
| HIGH-level input voltage | VIH | 4.2 | 3.2 | | V | VCC = 6.0 V; -40 °C to +125 °C; typ at 25 °C | 5 |
| LOW-level input voltage | VIL | | 0.8 | 0.5 | V | VCC = 2.0 V; -40 °C to +125 °C; typ at 25 °C | 5 |
| LOW-level input voltage | VIL | | 2.1 | 1.35 | V | VCC = 4.5 V; -40 °C to +125 °C; typ at 25 °C | 5 |
| LOW-level input voltage | VIL | | 2.8 | 1.8 | V | VCC = 6.0 V; -40 °C to +125 °C; typ at 25 °C | 5 |
| LOW-level output voltage | VOL | | 0 | 0.1 | V | VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V; -40 °C to +125 °C | 5 |
| LOW-level output voltage | VOL | | 0.15 | 0.4 | V | VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V; -40 °C to +125 °C | 5 |
| LOW-level output voltage | VOL | | 0.16 | 0.4 | V | VI = VIH or VIL; IO = 5.2 mA; VCC = 6.0 V; -40 °C to +125 °C | 5 |
| input leakage current | II | -1 | | 1 | μA | VI = VCC or GND; VCC = 6.0 V; -40 °C to +125 °C | 5 |
| OFF-state output current | IOZ | -10 | | 10 | μA | VI = VIL; VO = VCC or GND; VCC = 6.0 V; -40 °C to +125 °C | 5 |
| supply current | ICC | | | 40 | μA | VI = VCC or GND; IO = 0 A; VCC = 6.0 V; -40 °C to +125 °C | 5 |
| LOW to OFF-state propagation delay | tPLZ | | 20 | 135 | ns | nA to nY; see Fig. 6; VCC = 2.0 V; -40 °C to +125 °C | 6 |
| LOW to OFF-state propagation delay | tPLZ | | 11 | 27 | ns | nA to nY; see Fig. 6; VCC = 4.5 V; -40 °C to +125 °C | 6 |
| LOW to OFF-state propagation delay | tPLZ | | 10 | 23 | ns | nA to nY; see Fig. 6; VCC = 6.0 V; -40 °C to +125 °C | 6 |
| OFF-state to LOW propagation delay | tPZL | | 22 | 135 | ns | nA to nY; see Fig. 6; VCC = 2.0 V; -40 °C to +125 °C | 6 |
| OFF-state to LOW propagation delay | tPZL | | 9 | 27 | ns | nA to nY; see Fig. 6; VCC = 4.5 V; -40 °C to +125 °C | 6 |
| OFF-state to LOW propagation delay | tPZL | | 8 | 23 | ns | nA to nY; see Fig. 6; VCC = 6.0 V; -40 °C to +125 °C | 6 |
| HIGH to LOW output transition time | tTHL | | 18 | 110 | ns | see Fig. 6; VCC = 2.0 V; -40 °C to +125 °C | 6 |
| HIGH to LOW output transition time | tTHL | | 6 | 22 | ns | see Fig. 6; VCC = 4.5 V; -40 °C to +125 °C | 6 |
| HIGH to LOW output transition time | tTHL | | 5 | 19 | ns | see Fig. 6; VCC = 6.0 V; -40 °C to +125 °C | 6 |
## CAD (KiCad official)
- Symbol: `74HC05D`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files: `74hc05d-etched.step` / `74hc05d-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74hc05d.step` / `74hc05d.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/74HC05D.pdf) (13 pp, sha256 `8d6999747a1b3451`, retrieved 2026-10-15, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/74hc05d-datasheet.pdf)