component
74HC03NS14ARDQ
Public Made by Adomby adom
GR Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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74HC03NS14ARDQ
GR · Logic Gates · SOP-14
74HC03NS14ARDQ from GR, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input of gate 1; buffered input for a 2-input NAND gate operating from VCC = 2 V to 6 V. |
| 2 | 1B | input | Data input of gate 1; buffered input for a 2-input NAND gate operating from VCC = 2 V to 6 V. |
| 3 | 1Y | output | Open-drain output of gate 1; per the truth table it is low only when both inputs are high and high-impedance (Z) otherwise. |
| 4 | 2A | input | Data input of gate 2; buffered input for a 2-input NAND gate operating from VCC = 2 V to 6 V. |
| 5 | 2B | input | Data input of gate 2; buffered input for a 2-input NAND gate operating from VCC = 2 V to 6 V. |
| 6 | 2Y | output | Open-drain output of gate 2; per the truth table it is low only when both inputs are high and high-impedance (Z) otherwise. |
| 7 | GND | power_in | Ground reference; all voltages are referenced to GND (0 V). |
| 8 | 3Y | output | Open-drain output of gate 3; per the truth table it is low only when both inputs are high and high-impedance (Z) otherwise. |
| 9 | 3A | input | Data input of gate 3; buffered input for a 2-input NAND gate operating from VCC = 2 V to 6 V. |
| 10 | 3B | input | Data input of gate 3; buffered input for a 2-input NAND gate operating from VCC = 2 V to 6 V. |
| 11 | 4Y | output | Open-drain output of gate 4; per the truth table it is low only when both inputs are high and high-impedance (Z) otherwise. |
| 12 | 4A | input | Data input of gate 4; buffered input for a 2-input NAND gate operating from VCC = 2 V to 6 V. |
| 13 | 4B | input | Data input of gate 4; buffered input for a 2-input NAND gate operating from VCC = 2 V to 6 V. |
| 14 | VCC | power_in | Supply voltage; the datasheet specifies operation from 2 V to 6 V with an absolute maximum of 7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GR |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC | -0.5 | 7 | V | 3 | ||
| Power Dissipation | PD | 500 | mW | 3 | |||
| Junction Temperature | TJ | 125 | ℃ | 3 | |||
| Operating Temperature | TOP | -40 | 85 | ℃ | 3 | ||
| Supply Voltage (wide operating range) | VCC | 2 | 6 | V | Features: wide operating voltage range | 1 | |
| Operating Temperature (wide operating range) | TOP | -40 | 85 | ℃ | Features: wide operating temperature range | 1 | |
| High Level Input Voltage | VIH | 1.5 | V | VCC=2V | 3 | ||
| High Level Input Voltage | VIH | 3.15 | V | VCC=4.5V | 3 | ||
| High Level Input Voltage | VIH | 4.2 | V | VCC=6V | 3 | ||
| Low Level Input Voltage | VIL | 0.5 | V | VCC=2V | 3 | ||
| Low Level Input Voltage | VIL | 1.35 | V | VCC=4.5V | 3 | ||
| Low Level Input Voltage | VIL | 1.8 | V | VCC=6V | 3 | ||
| Low Level Output Voltage | VOL | 0.1 | V | VCC=2V, IO=20uA | 3 | ||
| Low Level Output Voltage | VOL | 0.3 | V | VCC=4.5V, IO=4mA | 3 | ||
| Input Leakage Current | II | -1.5 | 0 | 1.5 | uA | VCC=6V, VI=VCC or GND | 3 |
| Output Leakage Current | IOH | -10 | 0 | 10 | uA | VCC=6V, VO=VCC or GND | 3 |
| Quiescent Supply Current | ICC | 0 | 10 | uA | VCC=6V, VI=VCC/GND | 3 |
CAD (KiCad official)
- Symbol:
74HC03NS14ARDQ - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files:
74hc03ns14ardq-etched.step/74hc03ns14ardq-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc03ns14ardq.step/74hc03ns14ardq.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: GR datasheet (6 pp, sha256
074c56ce919f0416, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 74HC03NS14ARDQ
**GR** · Logic Gates · SOP-14
74HC03NS14ARDQ from GR, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input of gate 1; buffered input for a 2-input NAND gate operating from VCC = 2 V to 6 V. |
| 2 | 1B | input | Data input of gate 1; buffered input for a 2-input NAND gate operating from VCC = 2 V to 6 V. |
| 3 | 1Y | output | Open-drain output of gate 1; per the truth table it is low only when both inputs are high and high-impedance (Z) otherwise. |
| 4 | 2A | input | Data input of gate 2; buffered input for a 2-input NAND gate operating from VCC = 2 V to 6 V. |
| 5 | 2B | input | Data input of gate 2; buffered input for a 2-input NAND gate operating from VCC = 2 V to 6 V. |
| 6 | 2Y | output | Open-drain output of gate 2; per the truth table it is low only when both inputs are high and high-impedance (Z) otherwise. |
| 7 | GND | power_in | Ground reference; all voltages are referenced to GND (0 V). |
| 8 | 3Y | output | Open-drain output of gate 3; per the truth table it is low only when both inputs are high and high-impedance (Z) otherwise. |
| 9 | 3A | input | Data input of gate 3; buffered input for a 2-input NAND gate operating from VCC = 2 V to 6 V. |
| 10 | 3B | input | Data input of gate 3; buffered input for a 2-input NAND gate operating from VCC = 2 V to 6 V. |
| 11 | 4Y | output | Open-drain output of gate 4; per the truth table it is low only when both inputs are high and high-impedance (Z) otherwise. |
| 12 | 4A | input | Data input of gate 4; buffered input for a 2-input NAND gate operating from VCC = 2 V to 6 V. |
| 13 | 4B | input | Data input of gate 4; buffered input for a 2-input NAND gate operating from VCC = 2 V to 6 V. |
| 14 | VCC | power_in | Supply voltage; the datasheet specifies operation from 2 V to 6 V with an absolute maximum of 7 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GR |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC | -0.5 | | 7 | V | | 3 |
| Power Dissipation | PD | | | 500 | mW | | 3 |
| Junction Temperature | TJ | | | 125 | ℃ | | 3 |
| Operating Temperature | TOP | -40 | | 85 | ℃ | | 3 |
| Supply Voltage (wide operating range) | VCC | 2 | | 6 | V | Features: wide operating voltage range | 1 |
| Operating Temperature (wide operating range) | TOP | -40 | | 85 | ℃ | Features: wide operating temperature range | 1 |
| High Level Input Voltage | VIH | 1.5 | | | V | VCC=2V | 3 |
| High Level Input Voltage | VIH | 3.15 | | | V | VCC=4.5V | 3 |
| High Level Input Voltage | VIH | 4.2 | | | V | VCC=6V | 3 |
| Low Level Input Voltage | VIL | | | 0.5 | V | VCC=2V | 3 |
| Low Level Input Voltage | VIL | | | 1.35 | V | VCC=4.5V | 3 |
| Low Level Input Voltage | VIL | | | 1.8 | V | VCC=6V | 3 |
| Low Level Output Voltage | VOL | | | 0.1 | V | VCC=2V, IO=20uA | 3 |
| Low Level Output Voltage | VOL | | | 0.3 | V | VCC=4.5V, IO=4mA | 3 |
| Input Leakage Current | II | -1.5 | 0 | 1.5 | uA | VCC=6V, VI=VCC or GND | 3 |
| Output Leakage Current | IOH | -10 | 0 | 10 | uA | VCC=6V, VO=VCC or GND | 3 |
| Quiescent Supply Current | ICC | | 0 | 10 | uA | VCC=6V, VI=VCC/GND | 3 |
## CAD (KiCad official)
- Symbol: `74HC03NS14ARDQ`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files: `74hc03ns14ardq-etched.step` / `74hc03ns14ardq-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74hc03ns14ardq.step` / `74hc03ns14ardq.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [GR datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603388394831556608) (6 pp, sha256 `074c56ce919f0416`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/74hc03ns14ardq-datasheet.pdf)