# 74HC03MT

**HGSEMI** · Logic Gates · TSSOP-14

74HC03MT from HGSEMI, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Input channel 1, input A of the first NAND gate, which performs Y = A ● B in positive logic. |
| 2 | 1B | input | Input channel 1, input B of the first NAND gate, which performs Y = A ● B in positive logic. |
| 3 | 1Y | output | Output channel 1, an open-drain output that can sink current to GND but cannot source current from VCC and needs an external pull-up. |
| 4 | 2A | input | Input channel 2, input A of the second NAND gate, which performs Y = A ● B in positive logic. |
| 5 | 2B | input | Input channel 2, input B of the second NAND gate, which performs Y = A ● B in positive logic. |
| 6 | 2Y | output | Output channel 2, an open-drain output that can sink current to GND but cannot source current from VCC and needs an external pull-up. |
| 7 | GND | power_in | Ground reference for the device; the open-drain outputs sink current to this pin. |
| 8 | 3Y | output | Output channel 3, an open-drain output that can sink current to GND but cannot source current from VCC and needs an external pull-up. |
| 9 | 3A | input | Input channel 3, input A of the third NAND gate, which performs Y = A ● B in positive logic. |
| 10 | 3B | input | Input channel 3, input B of the third NAND gate, which performs Y = A ● B in positive logic. |
| 11 | 4Y | output | Output channel 4, an open-drain output that can sink current to GND but cannot source current from VCC and needs an external pull-up. |
| 12 | 4A | input | Input channel 4, input A of the fourth NAND gate, which performs Y = A ● B in positive logic. |
| 13 | 4B | input | Input channel 4, input B of the fourth NAND gate, which performs Y = A ● B in positive logic. |
| 14 | VCC | power_in | Positive supply; the recommended supply range is 2 V to 6 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | HGSEMI |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 |  | 7 | V |  | 3 |
| Input clamp current | IIK | -20 |  | 20 | mA | VI < 0 or VI > VCC | 3 |
| Output clamp current | IOK | -20 |  | 20 | mA | VO < 0 or VO > VCC | 3 |
| Continuous output current | IO | -25 |  | 25 | mA | VO = 0 to VCC | 3 |
| Continuous current through VCC or GND |  | -50 |  | 50 | mA |  | 3 |
| Junction temperature | TJ |  |  | 150 | °C |  | 3 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 3 |
| Lead temperature | TL |  |  | 260 | °C | Soldering, 10 seconds | 3 |
| Supply voltage | VCC | 2 | 5 | 6 | V |  | 3 |
| High-level input voltage | VIH | 1.5 |  |  | V | VCC = 2 V | 3 |
| High-level input voltage | VIH | 3.15 |  |  | V | VCC = 4.5 V | 3 |
| High-level input voltage | VIH | 4.2 |  |  | V | VCC = 6 V | 3 |
| Low-level input voltage | VIL |  |  | 0.5 | V | VCC = 2 V | 3 |
| Low-level input voltage | VIL |  |  | 1.35 | V | VCC = 4.5 V | 3 |
| Low-level input voltage | VIL |  |  | 1.8 | V | VCC = 6 V | 3 |
| Input transition rise and fall rate | Δt/Δv |  |  | 1000 | ns | VCC = 2 V | 3 |
| Input transition rise and fall rate | Δt/Δv |  |  | 500 | ns | VCC = 4.5 V | 3 |
| Input transition rise and fall rate | Δt/Δv |  |  | 400 | ns | VCC = 6 V | 3 |
| Operating free-air temperature | TA | -40 |  | 85 | °C |  | 3 |
| Output voltage IOH | IOH |  | 0.01 | 0.5 | µA | VI = VIH or VIL; VO = VCC; VCC 6 V; TA 25°C | 4 |
| Output voltage IOH | IOH |  |  | 5 | µA | VI = VIH or VIL; VO = VCC; VCC 6 V; TA -40°C to 85°C | 4 |
| Low-level output voltage | VOL |  | 0.002 | 0.1 | V | VI = VIH or VIL; IOL = 20 µA; VCC 2 V; TA 25°C | 4 |
| Low-level output voltage | VOL |  |  | 0.1 | V | VI = VIH or VIL; IOL = 20 µA; VCC 2 V; TA -40°C to 85°C | 4 |
| Low-level output voltage | VOL |  | 0.001 | 0.1 | V | VI = VIH or VIL; IOL = 20 µA; VCC 4.5 V; TA 25°C | 4 |
| Low-level output voltage | VOL |  | 0.17 | 0.26 | V | VI = VIH or VIL; IOL = 4 mA; VCC 4.5 V; TA 25°C | 4 |
| Low-level output voltage | VOL |  |  | 0.33 | V | VI = VIH or VIL; IOL = 4 mA; VCC 4.5 V; TA -40°C to 85°C | 4 |
| Low-level output voltage | VOL |  | 0.15 | 0.26 | V | VI = VIH or VIL; IOL = 5.2 mA; VCC 6 V; TA 25°C | 4 |
| Input leakage current | II | -0.1 |  | 0.1 | µA | VI = VCC or 0; VCC 6 V; TA 25°C | 4 |
| Input leakage current | II | -1 |  | 1 | µA | VI = VCC or 0; VCC 6 V; TA -40°C to 85°C | 4 |
| Supply current | ICC |  | 2 |  | µA | VI = VCC or 0; IO = 0; VCC 6 V; TA 25°C | 4 |
| Supply current | ICC |  |  | 20 | µA | VI = VCC or 0; IO = 0; VCC 6 V; TA -40°C to 85°C | 4 |
| Input capacitance | Ci |  | 3 | 10 | pF | VCC 2 V to 6 V; TA 25°C | 4 |
| Input capacitance | Ci |  |  | 10 | pF | VCC 2 V to 6 V; TA -40°C to 85°C | 4 |
| Propagation delay, low-to-high | tplh |  | 60 | 105 | ns | A or B to Y; VCC 2 V; TA 25°C | 5 |
| Propagation delay, low-to-high | tplh |  |  | 131 | ns | A or B to Y; VCC 2 V; TA -40°C to 85°C | 5 |
| Propagation delay, low-to-high | tplh |  | 13 | 25 | ns | A or B to Y; VCC 4.5 V; TA 25°C | 5 |
| Propagation delay, low-to-high | tplh |  |  | 31 | ns | A or B to Y; VCC 4.5 V; TA -40°C to 85°C | 5 |
| Propagation delay, low-to-high | tplh |  | 10 | 23 | ns | A or B to Y; VCC 6 V; TA 25°C | 5 |
| Propagation delay, low-to-high | tplh |  |  | 27 | ns | A or B to Y; VCC 6 V; TA -40°C to 85°C | 5 |
| Propagation delay, high-to-low | tphl |  | 50 | 100 | ns | A or B to Y; VCC 2 V; TA 25°C | 5 |
| Propagation delay, high-to-low | tphl |  |  | 125 | ns | A or B to Y; VCC 2 V; TA -40°C to 85°C | 5 |
| Propagation delay, high-to-low | tphl |  | 10 | 20 | ns | A or B to Y; VCC 4.5 V; TA 25°C | 5 |
| Propagation delay, high-to-low | tphl |  |  | 25 | ns | A or B to Y; VCC 4.5 V; TA -40°C to 85°C | 5 |
| Propagation delay, high-to-low | tphl |  | 8 | 17 | ns | A or B to Y; VCC 6 V; TA 25°C | 5 |
| Propagation delay, high-to-low | tphl |  |  | 21 | ns | A or B to Y; VCC 6 V; TA -40°C to 85°C | 5 |
| Transition time | tt |  | 38 | 75 | ns | Y; VCC 2 V; TA 25°C | 5 |
| Transition time | tt |  |  | 95 | ns | Y; VCC 2 V; TA -40°C to 85°C | 5 |
| Transition time | tt |  | 8 | 15 | ns | Y; VCC 4.5 V; TA 25°C | 5 |
| Transition time | tt |  |  | 19 | ns | Y; VCC 4.5 V; TA -40°C to 85°C | 5 |
| Transition time | tt |  | 6 | 13 | ns | Y; VCC 6 V; TA 25°C | 5 |
| Transition time | tt |  |  | 16 | ns | Y; VCC 6 V; TA -40°C to 85°C | 5 |
| Junction-to-ambient thermal resistance | RθJA |  | 151.7 |  | °C/W | TSSOP-14 | 4 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 79.4 |  | °C/W | TSSOP-14 | 4 |
| Junction-to-board thermal resistance | RθJB |  | 94.7 |  | °C/W | TSSOP-14 | 4 |
| Power dissipation capacitance per gate | Cpd |  | 20 |  | pF | No load; VCC 2 V to 6 V | 5 |

## CAD (KiCad official)

- Symbol: `74HC03MT`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `74hc03mt-etched.step` / `74hc03mt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74hc03mt.step` / `74hc03mt.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [HGSEMI datasheet](docs/74hc03mt-datasheet.pdf) (12 pp, sha256 `59efd34230dfb57b`, retrieved 2026-10-27, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `off` (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/74hc03mt-datasheet.pdf)