component
74HC02N
Public Made by Adomby adom
HGSEMI Logic Gates, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74HC02N
HGSEMI · Logic Gates · DIP-14
74HC02N from HGSEMI, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Y1 | output | Gate 1 output, high only when A1 and B1 are both low; drives 10 LSTTL loads. |
| 2 | A1 | input | Gate 1 input A; input voltage must stay between GND and VCC, unused inputs must be tied to GND or VCC. |
| 3 | B1 | input | Gate 1 input B; input voltage must stay between GND and VCC, unused inputs must be tied to GND or VCC. |
| 4 | Y2 | output | Gate 2 output, high only when A2 and B2 are both low; drives 10 LSTTL loads. |
| 5 | A2 | input | Gate 2 input A; input voltage must stay between GND and VCC, unused inputs must be tied to GND or VCC. |
| 6 | B2 | input | Gate 2 input B; input voltage must stay between GND and VCC, unused inputs must be tied to GND or VCC. |
| 7 | GND | power_in | Ground reference (0 V) for supply and all logic levels. |
| 8 | A3 | input | Gate 3 input A; input voltage must stay between GND and VCC, unused inputs must be tied to GND or VCC. |
| 9 | B3 | input | Gate 3 input B; input voltage must stay between GND and VCC, unused inputs must be tied to GND or VCC. |
| 10 | Y3 | output | Gate 3 output, high only when A3 and B3 are both low; drives 10 LSTTL loads. |
| 11 | A4 | input | Gate 4 input A; input voltage must stay between GND and VCC, unused inputs must be tied to GND or VCC. |
| 12 | B4 | input | Gate 4 input B; input voltage must stay between GND and VCC, unused inputs must be tied to GND or VCC. |
| 13 | Y4 | output | Gate 4 output, high only when A4 and B4 are both low; drives 10 LSTTL loads. |
| 14 | VCC | power_in | Positive supply, recommended 2.0 to 6.0 V, absolute maximum 7.0 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HGSEMI |
| Package | DIP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage (Referenced to GND) | VCC | 2 | 6 | V | 3 | ||
| DC Input Voltage, Output Voltage (Referenced to GND) | Vin, Vout | 0 | V | Maximum is VCC (symbolic) | 3 | ||
| Operating Temperature, All Package Types | TA | -40 | 85 | °C | 3 | ||
| Input Rise and Fall Time | tr, tf | 0 | 1000 | ns | VCC = 2.0 V; Figure 1 | 3 | |
| Input Rise and Fall Time | tr, tf | 0 | 500 | ns | VCC = 4.5 V; Figure 1 | 3 | |
| Input Rise and Fall Time | tr, tf | 0 | 400 | ns | VCC = 6.0 V; Figure 1 | 3 | |
| DC Supply Voltage (Referenced to GND) | VCC | -0.5 | 7 | V | 3 | ||
| DC Input Voltage (Referenced to GND) | Vin | -0.5 | V | Maximum is VCC + 0.5 V (symbolic) | 3 | ||
| DC Output Voltage (Referenced to GND) | Vout | -0.5 | V | Maximum is VCC + 0.5 V (symbolic) | 3 | ||
| DC Input Current | Iin | 20 | mA | 3 | |||
| DC Output Current | Iout | 25 | mA | 3 | |||
| DC Supply Current, VCC and GND Pins | ICC | 50 | mA | 3 | |||
| Storage Temperature | Tstg | -65 | 150 | °C | 3 | ||
| Minimum High-Level Input Voltage | VIH | 1.5 | V | VCC = 2.0 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; <=85 C column | 4 | ||
| Minimum High-Level Input Voltage | VIH | 2.1 | V | VCC = 3.0 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; <=85 C column | 4 | ||
| Minimum High-Level Input Voltage | VIH | 3.15 | V | VCC = 4.5 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; <=85 C column | 4 | ||
| Minimum High-Level Input Voltage | VIH | 4.2 | V | VCC = 6.0 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; <=85 C column | 4 | ||
| Maximum Low-Level Input Voltage | VIL | 0.5 | V | VCC = 2.0 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; <=85 C column | 4 | ||
| Maximum Low-Level Input Voltage | VIL | 0.9 | V | VCC = 3.0 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; <=85 C column | 4 | ||
| Maximum Low-Level Input Voltage | VIL | 1.35 | V | VCC = 4.5 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; <=85 C column | 4 | ||
| Maximum Low-Level Input Voltage | VIL | 1.8 | V | VCC = 6.0 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; <=85 C column | 4 | ||
| Minimum High-Level Output Voltage | VOH | 1.9 | V | VCC = 2.0 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA; <=85 C column | 4 | ||
| Minimum High-Level Output Voltage | VOH | 4.4 | V | VCC = 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA; <=85 C column | 4 | ||
| Minimum High-Level Output Voltage | VOH | 5.9 | V | VCC = 6.0 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA; <=85 C column | 4 | ||
| Minimum High-Level Output Voltage | VOH | 2.34 | V | VCC = 3.0 V; Vin = VIH or VIL; /Iout/ ≤ 4.0 mA (as printed); <=85 C column | 4 | ||
| Minimum High-Level Output Voltage | VOH | 3.84 | V | VCC = 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 4.0 mA (as printed); <=85 C column | 4 | ||
| Minimum High-Level Output Voltage | VOH | 5.34 | V | VCC = 6.0 V; Vin = VIH or VIL; /Iout/ ≤ 5.2 mA (as printed); <=85 C column | 4 | ||
| Maximum Low-Level Output Voltage | VOL | 0.1 | V | VCC = 2.0 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA; <=85 C column | 4 | ||
| Maximum Low-Level Output Voltage | VOL | 0.33 | V | VCC = 3.0 V; Vin = VIH or VIL; /Iout/ ≤ 4.0 mA (as printed); <=85 C column | 4 | ||
| Maximum Input Leakage Current | Iin | 1 | µA | VCC = 6.0 V; Vin = VCC or GND; <=85 C column | 4 | ||
| Maximum Quiescent Supply Current (per Package) | ICC | 20 | µA | VCC = 6.0 V; Vin = VCC or GND; /Iout/ = 0 µA; <=85 C column | 4 | ||
| Maximum Propagation Delay, Input A or B to Output Y | tPLH, tPHL | 95 | ns | VCC = 2.0 V; CL = 50 pF; Input tr = tf = 6.0 ns; <=85 C column | 4 | ||
| Maximum Propagation Delay, Input A or B to Output Y | tPLH, tPHL | 40 | ns | VCC = 3.0 V; CL = 50 pF; Input tr = tf = 6.0 ns; <=85 C column | 4 | ||
| Maximum Propagation Delay, Input A or B to Output Y | tPLH, tPHL | 19 | ns | VCC = 4.5 V; CL = 50 pF; Input tr = tf = 6.0 ns; <=85 C column | 4 | ||
| Maximum Propagation Delay, Input A or B to Output Y | tPLH, tPHL | 16 | ns | VCC = 6.0 V; CL = 50 pF; Input tr = tf = 6.0 ns; <=85 C column | 4 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 95 | ns | VCC = 2.0 V; CL = 50 pF; Input tr = tf = 6.0 ns; <=85 C column | 4 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 40 | ns | VCC = 3.0 V; CL = 50 pF; Input tr = tf = 6.0 ns; <=85 C column | 4 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 19 | ns | VCC = 4.5 V; CL = 50 pF; Input tr = tf = 6.0 ns; <=85 C column | 4 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 16 | ns | VCC = 6.0 V; CL = 50 pF; Input tr = tf = 6.0 ns; <=85 C column | 4 | ||
| Maximum Input Capacitance | Cin | 10 | pF | <=85 C column | 4 | ||
| Power Dissipation Capacitance (Per Gate) | CPD | 22 | pF | Typical @ 25 C, VCC = 5.0 V | 4 |
CAD (KiCad official)
- Symbol:
74HC02N - Footprint:
Package_DIP:DIP-14_W7.62mm - 3D model: DIP-14 (KiCad packages3D, STEP)
- 3D model files:
74hc02n-etched.step/74hc02n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc02n.step/74hc02n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HGSEMI datasheet (9 pp, sha256
868940124e153af6, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).