← Commit history

pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left)

Ray ·8289d46138 ·1mo ago ·parent d93c0b2
2 files changed +447−1
package.json+2−1
@@ -24,6 +24,7 @@     "docs/hero.png",     "docs/74hc02d-datasheet.pdf",     "viewers/symbol.html",-    "viewers/footprint.html"+    "viewers/footprint.html",+    "pads.json"   ] }\ No newline at end of file
pads.jsonadded+445
@@ -0,0 +1,445 @@+{+ "schema": "adom.pads/1",+ "slug": "74hc02d",+ "footprint": "SOIC-14_3.9x8.7mm_P1.27mm",+ "generated_from": {+  "footprint": "SOIC-14_3.9x8.7mm_P1.27mm@sha256:a885b619b22880c9",+  "pins": "page.json:component.pins",+  "overrides": null+ },+ "pin1": {+  "pad": "1",+  "at": [+   -2.475,+   -3.81+  ],+  "corner": "top-left",+  "source": "silk-marker",+  "derived_from": "SOIC-14_3.9x8.7mm_P1.27mm@sha256:a885b619b22880c9"+ },+ "pad_count": 14,+ "paste_apertures": 0,+ "issues": [],+ "pads": [+  {+   "pad": "1",+   "kind": "smd",+   "shape": "roundrect",+   "at": [+    -2.475,+    -3.81+   ],+   "rot": 0.0,+   "size": [+    1.95,+    0.6+   ],+   "layers": [+    "F.Cu",+    "F.Mask",+    "F.Paste"+   ],+   "thermal": false,+   "pin": "1",+   "name": "1Y",+   "type": "output",+   "description": "Data output of gate 1 (NOR of 1A and 1B). CMOS push-pull output, can drive IO up to -5.2 mA (source) / 5.2 mA (sink) at VCC = 6.0 V.",+   "is_pin1": true,+   "source": {+    "geometry": "SOIC-14_3.9x8.7mm_P1.27mm.kicad_mod",+    "meaning": "page.json:component.pins",+    "correspondence": "kicad: symbol pin number == pad name"+   }+  },+  {+   "pad": "2",+   "kind": "smd",+   "shape": "roundrect",+   "at": [+    -2.475,+    -2.54+   ],+   "rot": 0.0,+   "size": [+    1.95,+    0.6+   ],+   "layers": [+    "F.Cu",+    "F.Mask",+    "F.Paste"+   ],+   "thermal": false,+   "pin": "2",+   "name": "1A",+   "type": "input",+   "description": "Data input A of gate 1. CMOS logic input with clamp diodes; input voltage 0 to VCC recommended, VIH >= 3.15 V at VCC = 4.5 V (74HC02).",+   "is_pin1": false,+   "source": {+    "geometry": "SOIC-14_3.9x8.7mm_P1.27mm.kicad_mod",+    "meaning": "page.json:component.pins",+    "correspondence": "kicad: symbol pin number == pad name"+   }+  },+  {+   "pad": "3",+   "kind": "smd",+   "shape": "roundrect",+   "at": [+    -2.475,+    -1.27+   ],+   "rot": 0.0,+   "size": [+    1.95,+    0.6+   ],+   "layers": [+    "F.Cu",+    "F.Mask",+    "F.Paste"+   ],+   "thermal": false,+   "pin": "3",+   "name": "1B",+   "type": "input",+   "description": "Data input B of gate 1. CMOS logic input with clamp diodes; input voltage 0 to VCC recommended.",+   "is_pin1": false,+   "source": {+    "geometry": "SOIC-14_3.9x8.7mm_P1.27mm.kicad_mod",+    "meaning": "page.json:component.pins",+    "correspondence": "kicad: symbol pin number == pad name"+   }+  },+  {+   "pad": "4",+   "kind": "smd",+   "shape": "roundrect",+   "at": [+    -2.475,+    0.0+   ],+   "rot": 0.0,+   "size": [+    1.95,+    0.6+   ],+   "layers": [+    "F.Cu",+    "F.Mask",+    "F.Paste"+   ],+   "thermal": false,+   "pin": "4",+   "name": "2Y",+   "type": "output",+   "description": "Data output of gate 2 (NOR of 2A and 2B). CMOS push-pull output.",+   "is_pin1": false,+   "source": {+    "geometry": "SOIC-14_3.9x8.7mm_P1.27mm.kicad_mod",+    "meaning": "page.json:component.pins",+    "correspondence": "kicad: symbol pin number == pad name"+   }+  },+  {+   "pad": "5",+   "kind": "smd",+   "shape": "roundrect",+   "at": [+    -2.475,+    1.27+   ],+   "rot": 0.0,+   "size": [+    1.95,+    0.6+   ],+   "layers": [+    "F.Cu",+    "F.Mask",+    "F.Paste"+   ],+   "thermal": false,+   "pin": "5",+   "name": "2A",+   "type": "input",+   "description": "Data input A of gate 2. CMOS logic input with clamp diodes.",+   "is_pin1": false,+   "source": {+    "geometry": "SOIC-14_3.9x8.7mm_P1.27mm.kicad_mod",+    "meaning": "page.json:component.pins",+    "correspondence": "kicad: symbol pin number == pad name"+   }+  },+  {+   "pad": "6",+   "kind": "smd",+   "shape": "roundrect",+   "at": [+    -2.475,+    2.54+   ],+   "rot": 0.0,+   "size": [+    1.95,+    0.6+   ],+   "layers": [+    "F.Cu",+    "F.Mask",+    "F.Paste"+   ],+   "thermal": false,+   "pin": "6",+   "name": "2B",+   "type": "input",+   "description": "Data input B of gate 2. CMOS logic input with clamp diodes.",+   "is_pin1": false,+   "source": {+    "geometry": "SOIC-14_3.9x8.7mm_P1.27mm.kicad_mod",+    "meaning": "page.json:component.pins",+    "correspondence": "kicad: symbol pin number == pad name"+   }+  },+  {+   "pad": "7",+   "kind": "smd",+   "shape": "roundrect",+   "at": [+    -2.475,+    3.81+   ],+   "rot": 0.0,+   "size": [+    1.95,+    0.6+   ],+   "layers": [+    "F.Cu",+    "F.Mask",+    "F.Paste"+   ],+   "thermal": false,+   "pin": "7",+   "name": "GND",+   "type": "power_in",+   "description": "Ground reference (0 V).",+   "is_pin1": false,+   "source": {+    "geometry": "SOIC-14_3.9x8.7mm_P1.27mm.kicad_mod",+    "meaning": "page.json:component.pins",+    "correspondence": "kicad: symbol pin number == pad name"+   }+  },+  {+   "pad": "8",+   "kind": "smd",+   "shape": "roundrect",+   "at": [+    2.475,+    3.81+   ],+   "rot": 0.0,+   "size": [+    1.95,+    0.6+   ],+   "layers": [+    "F.Cu",+    "F.Mask",+    "F.Paste"+   ],+   "thermal": false,+   "pin": "8",+   "name": "3A",+   "type": "input",+   "description": "Data input A of gate 3. CMOS logic input with clamp diodes.",+   "is_pin1": false,+   "source": {+    "geometry": "SOIC-14_3.9x8.7mm_P1.27mm.kicad_mod",+    "meaning": "page.json:component.pins",+    "correspondence": "kicad: symbol pin number == pad name"+   }+  },+  {+   "pad": "9",+   "kind": "smd",+   "shape": "roundrect",+   "at": [+    2.475,+    2.54+   ],+   "rot": 0.0,+   "size": [+    1.95,+    0.6+   ],+   "layers": [+    "F.Cu",+    "F.Mask",+    "F.Paste"+   ],+   "thermal": false,+   "pin": "9",+   "name": "3B",+   "type": "input",+   "description": "Data input B of gate 3. CMOS logic input with clamp diodes.",+   "is_pin1": false,+   "source": {+    "geometry": "SOIC-14_3.9x8.7mm_P1.27mm.kicad_mod",+    "meaning": "page.json:component.pins",+    "correspondence": "kicad: symbol pin number == pad name"+   }+  },+  {+   "pad": "10",+   "kind": "smd",+   "shape": "roundrect",+   "at": [+    2.475,+    1.27+   ],+   "rot": 0.0,+   "size": [+    1.95,+    0.6+   ],+   "layers": [+    "F.Cu",+    "F.Mask",+    "F.Paste"+   ],+   "thermal": false,+   "pin": "10",+   "name": "3Y",+   "type": "output",+   "description": "Data output of gate 3 (NOR of 3A and 3B). CMOS push-pull output.",+   "is_pin1": false,+   "source": {+    "geometry": "SOIC-14_3.9x8.7mm_P1.27mm.kicad_mod",+    "meaning": "page.json:component.pins",+    "correspondence": "kicad: symbol pin number == pad name"+   }+  },+  {+   "pad": "11",+   "kind": "smd",+   "shape": "roundrect",+   "at": [+    2.475,+    0.0+   ],+   "rot": 0.0,+   "size": [+    1.95,+    0.6+   ],+   "layers": [+    "F.Cu",+    "F.Mask",+    "F.Paste"+   ],+   "thermal": false,+   "pin": "11",+   "name": "4A",+   "type": "input",+   "description": "Data input A of gate 4. CMOS logic input with clamp diodes.",+   "is_pin1": false,+   "source": {+    "geometry": "SOIC-14_3.9x8.7mm_P1.27mm.kicad_mod",+    "meaning": "page.json:component.pins",+    "correspondence": "kicad: symbol pin number == pad name"+   }+  },+  {+   "pad": "12",+   "kind": "smd",+   "shape": "roundrect",+   "at": [+    2.475,+    -1.27+   ],+   "rot": 0.0,+   "size": [+    1.95,+    0.6+   ],+   "layers": [+    "F.Cu",+    "F.Mask",+    "F.Paste"+   ],+   "thermal": false,+   "pin": "12",+   "name": "4B",+   "type": "input",+   "description": "Data input B of gate 4. CMOS logic input with clamp diodes.",+   "is_pin1": false,+   "source": {+    "geometry": "SOIC-14_3.9x8.7mm_P1.27mm.kicad_mod",+    "meaning": "page.json:component.pins",+    "correspondence": "kicad: symbol pin number == pad name"+   }+  },+  {+   "pad": "13",+   "kind": "smd",+   "shape": "roundrect",+   "at": [+    2.475,+    -2.54+   ],+   "rot": 0.0,+   "size": [+    1.95,+    0.6+   ],+   "layers": [+    "F.Cu",+    "F.Mask",+    "F.Paste"+   ],+   "thermal": false,+   "pin": "13",+   "name": "4Y",+   "type": "output",+   "description": "Data output of gate 4 (NOR of 4A and 4B). CMOS push-pull output.",+   "is_pin1": false,+   "source": {+    "geometry": "SOIC-14_3.9x8.7mm_P1.27mm.kicad_mod",+    "meaning": "page.json:component.pins",+    "correspondence": "kicad: symbol pin number == pad name"+   }+  },+  {+   "pad": "14",+   "kind": "smd",+   "shape": "roundrect",+   "at": [+    2.475,+    -3.81+   ],+   "rot": 0.0,+   "size": [+    1.95,+    0.6+   ],+   "layers": [+    "F.Cu",+    "F.Mask",+    "F.Paste"+   ],+   "thermal": false,+   "pin": "14",+   "name": "VCC",+   "type": "power_in",+   "description": "Positive supply voltage. Operating range 2.0 V to 6.0 V (74HC02); absolute max +7 V.",+   "is_pin1": false,+   "source": {+    "geometry": "SOIC-14_3.9x8.7mm_P1.27mm.kicad_mod",+    "meaning": "page.json:component.pins",+    "correspondence": "kicad: symbol pin number == pad name"+   }+  }+ ]+}\ No newline at end of file