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74HC02BQ-Q100

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Nexperia Logic Gates, DHVQFN-14-EP(2.5x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74HC02BQ-Q100

Nexperia · Logic Gates · DHVQFN-14-EP(2.5x3)

74HC02BQ-Q100 from Nexperia, in a DHVQFN-14-EP(2.5x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1Y output Data output of NOR gate 1; Y is HIGH only when both inputs 1A and 1B are LOW (Table 3).
2 1A input Data input A of NOR gate 1; clamp diodes allow current-limiting resistors for inputs above VCC, with input clamping current limited to ±20 mA (Table 4).
3 1B input Data input B of NOR gate 1; clamp diodes allow current-limiting resistors for inputs above VCC, with input clamping current limited to ±20 mA (Table 4).
4 2Y output Data output of NOR gate 2; Y is HIGH only when both inputs 2A and 2B are LOW (Table 3).
5 2A input Data input A of NOR gate 2; clamp diodes allow current-limiting resistors for inputs above VCC, with input clamping current limited to ±20 mA (Table 4).
6 2B input Data input B of NOR gate 2; clamp diodes allow current-limiting resistors for inputs above VCC, with input clamping current limited to ±20 mA (Table 4).
7 GND power_in Ground (0 V) reference for all voltages in the datasheet.
8 3A input Data input A of NOR gate 3; clamp diodes allow current-limiting resistors for inputs above VCC, with input clamping current limited to ±20 mA (Table 4).
9 3B input Data input B of NOR gate 3; clamp diodes allow current-limiting resistors for inputs above VCC, with input clamping current limited to ±20 mA (Table 4).
10 3Y output Data output of NOR gate 3; Y is HIGH only when both inputs 3A and 3B are LOW (Table 3).
11 4A input Data input A of NOR gate 4; clamp diodes allow current-limiting resistors for inputs above VCC, with input clamping current limited to ±20 mA (Table 4).
12 4B input Data input B of NOR gate 4; clamp diodes allow current-limiting resistors for inputs above VCC, with input clamping current limited to ±20 mA (Table 4).
13 4Y output Data output of NOR gate 4; Y is HIGH only when both inputs 4A and 4B are LOW (Table 3).
14 VCC power_in Supply voltage: 2.0 V to 6.0 V for 74HC02-Q100 and 4.5 V to 5.5 V for 74HCT02-Q100 (recommended operating conditions); absolute maximum -0.5 V to +7 V.
15 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Nexperia
Package DHVQFN-14-EP(2.5x3)
Category Logic
Pins 15

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC 2 5 6 V 74HC02-Q100 column 3
input voltage VI 0 V max = VCC 3
output voltage VO 0 V max = VCC 3
ambient temperature Tamb -40 125 °C 3
input transition rise and fall rate Δt/ΔV 625 ns/V VCC = 2.0 V 3
input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 3
input transition rise and fall rate Δt/ΔV 83 ns/V VCC = 6.0 V 3
supply voltage VCC -0.5 7 V 3
input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 3
output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 3
output current IO -25 25 mA -0.5 V < VO < VCC + 0.5 V 3
supply current ICC 50 mA 3
ground current IGND -50 mA 3
storage temperature Tstg -65 150 °C 3
total power dissipation Ptot 500 mW SOT762-1 (DHVQFN14); derates 9.6 mW/K above 98 °C 3
HIGH-level input voltage VIH 1.5 1.2 V VCC = 2.0 V; min at -40 °C to +125 °C; typ at 25 °C 4
HIGH-level input voltage VIH 3.15 2.4 V VCC = 4.5 V; min at -40 °C to +125 °C; typ at 25 °C 4
HIGH-level input voltage VIH 4.2 3.2 V VCC = 6.0 V; min at -40 °C to +125 °C; typ at 25 °C 4
LOW-level input voltage VIL 0.8 0.5 V VCC = 2.0 V; max at -40 °C to +125 °C; typ at 25 °C 4
LOW-level input voltage VIL 2.1 1.35 V VCC = 4.5 V; max at -40 °C to +125 °C; typ at 25 °C 4
LOW-level input voltage VIL 2.8 1.8 V VCC = 6.0 V; max at -40 °C to +125 °C; typ at 25 °C 4
HIGH-level output voltage VOH 1.9 2 V VI = VIH or VIL; IO = -20 μA; VCC = 2.0 V; min at -40 °C to +125 °C 4
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V; min at -40 °C to +125 °C 4
HIGH-level output voltage VOH 5.9 6 V VI = VIH or VIL; IO = -20 μA; VCC = 6.0 V; min at -40 °C to +125 °C 4
HIGH-level output voltage VOH 3.7 4.32 V VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V; min at -40 °C to +125 °C 4
HIGH-level output voltage VOH 5.2 5.81 V VI = VIH or VIL; IO = -5.2 mA; VCC = 6.0 V; min at -40 °C to +125 °C 4
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V; max at -40 °C to +125 °C 4
LOW-level output voltage VOL 0.15 0.4 V VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V; max at -40 °C to +125 °C 4
LOW-level output voltage VOL 0.16 0.4 V VI = VIH or VIL; IO = 5.2 mA; VCC = 6.0 V; max at -40 °C to +125 °C 4
input leakage current II -1 1 μA VI = VCC or GND; VCC = 6.0 V; ±1 μA at -40 °C to +125 °C 4
supply current ICC 40 μA VI = VCC or GND; IO = 0 A; VCC = 6.0 V; max at -40 °C to +125 °C 4
propagation delay nA, nB to nY tpd 25 135 ns VCC = 2.0 V; CL = 50 pF; see Fig. 4; max at -40 °C to +125 °C; typ at 25 °C 5
propagation delay nA, nB to nY tpd 9 27 ns VCC = 4.5 V; CL = 50 pF; see Fig. 4; max at -40 °C to +125 °C; typ at 25 °C 5
propagation delay nA, nB to nY tpd 7 23 ns VCC = 6.0 V; CL = 50 pF; see Fig. 4; max at -40 °C to +125 °C; typ at 25 °C 5
transition time tt 19 110 ns VCC = 2.0 V; CL = 50 pF; see Fig. 4; max at -40 °C to +125 °C; typ at 25 °C 5
transition time tt 7 22 ns VCC = 4.5 V; CL = 50 pF; see Fig. 4; max at -40 °C to +125 °C; typ at 25 °C 5
transition time tt 6 19 ns VCC = 6.0 V; CL = 50 pF; see Fig. 4; max at -40 °C to +125 °C; typ at 25 °C 5

CAD (KiCad official)

  • Symbol: 74HC02BQ-Q100
  • Footprint: Package_DFN_QFN:DHVQFN-14-1EP_2.5x3mm_P0.5mm_EP1x1.5mm
  • 3D model: DHVQFN-14-EP(2.5x3), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: 74hc02bq-q100-etched.step / 74hc02bq-q100-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc02bq-q100.step / 74hc02bq-q100.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (13 pp, sha256 b3b6767f1a8f2df6, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF