component
74HC00PW
Public Made by Adomby adom
Nexperia Logic ICs, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74HC00PW
Nexperia · Logic ICs · TSSOP-14
74HC00PW from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input of NAND gate 1; per Table 5 the input voltage range is 0 V to VCC, and a LOW level here with the other input X gives a HIGH output (Table 3). |
| 2 | 1B | input | Data input of NAND gate 1; per Table 5 the input voltage range is 0 V to VCC, and the output 1Y goes LOW only when both 1A and 1B are HIGH (Table 3). |
| 3 | 1Y | output | Data output of NAND gate 1; output current is limited to ±25 mA and output voltage must stay between -0.5 V and VCC + 0.5 V (Table 4). |
| 4 | 2A | input | Data input of NAND gate 2; per Table 5 the input voltage range is 0 V to VCC, and a LOW level here forces output 2Y HIGH (Table 3). |
| 5 | 2B | input | Data input of NAND gate 2; per Table 5 the input voltage range is 0 V to VCC, and the output 2Y goes LOW only when both 2A and 2B are HIGH (Table 3). |
| 6 | 2Y | output | Data output of NAND gate 2; output current is limited to ±25 mA and output voltage must stay between -0.5 V and VCC + 0.5 V (Table 4). |
| 7 | GND | power_in | Ground (0 V); all voltage ratings in the datasheet are referenced to this pin. |
| 8 | 3Y | output | Data output of NAND gate 3; output current is limited to ±25 mA and output voltage must stay between -0.5 V and VCC + 0.5 V (Table 4). |
| 9 | 3A | input | Data input of NAND gate 3; per Table 5 the input voltage range is 0 V to VCC, and a LOW level here forces output 3Y HIGH (Table 3). |
| 10 | 3B | input | Data input of NAND gate 3; per Table 5 the input voltage range is 0 V to VCC, and the output 3Y goes LOW only when both 3A and 3B are HIGH (Table 3). |
| 11 | 4Y | output | Data output of NAND gate 4; output current is limited to ±25 mA and output voltage must stay between -0.5 V and VCC + 0.5 V (Table 4). |
| 12 | 4A | input | Data input of NAND gate 4; per Table 5 the input voltage range is 0 V to VCC, and a LOW level here forces output 4Y HIGH (Table 3). |
| 13 | 4B | input | Data input of NAND gate 4; per Table 5 the input voltage range is 0 V to VCC, and the output 4Y goes LOW only when both 4A and 4B are HIGH (Table 3). |
| 14 | VCC | power_in | Supply voltage: 2.0 V to 6.0 V for 74HC00 and 4.5 V to 5.5 V for 74HCT00 recommended, with an absolute maximum of 7 V (Tables 4 and 5). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-14 |
| Category | Logic ICs |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (absolute maximum) | VCC | -0.5 | 7 | V | 4 | ||
| Input clamping current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V; see note [1] | 4 | |
| Output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V; see note [1] | 4 | |
| Output current | IO | -25 | 25 | mA | -0.5 V < VO < VCC + 0.5 V | 4 | |
| Supply current (absolute maximum) | ICC | 50 | mA | 4 | |||
| Ground current | IGND | -50 | mA | 4 | |||
| Supply voltage (74HC00) | VCC | 2 | 5 | 6 | V | 4 | |
| Input voltage | VI | 0 | V | maximum printed as VCC | 4 | ||
| Output voltage | VO | 0 | V | maximum printed as VCC | 4 | ||
| Ambient temperature | Tamb | -40 | 25 | 125 | °C | 4 | |
| LOW-level output voltage | VOL | 0 | 0.1 | V | VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V; max at -40 °C to +125 °C | 5 | |
| Input leakage current | II | -1 | 1 | μA | VI = VCC or GND; VCC = 6.0 V; min/max at -40 °C to +125 °C | 5 | |
| Supply current | ICC | 40 | μA | VI = VCC or GND; IO = 0 A; VCC = 6.0 V; max at -40 °C to +125 °C | 5 | ||
| Propagation delay nA, nB to nY | tpd | 9 | 27 | ns | VCC = 4.5 V; CL = 50 pF; see Fig. 4; max at -40 °C to +125 °C | 6 | |
| Propagation delay nA, nB to nY | tpd | 7 | 23 | ns | VCC = 6.0 V; CL = 50 pF; see Fig. 4; max at -40 °C to +125 °C | 6 | |
| Transition time | tt | 6 | 19 | ns | VCC = 6.0 V; see Fig. 4; max at -40 °C to +125 °C | 6 |
CAD (KiCad official)
- Symbol:
74HC00PW - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
74hc00pw-etched.step/74hc00pw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc00pw.step/74hc00pw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (12 pp, sha256
a01759669120aa7d, retrieved 2026-10-21, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).