component
74HC00D
Public Made by Adomby adom
Nexperia Gates, SOIC-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left)
2 files changed
+447−1
package.json+2−1@@ -24,6 +24,7 @@ "docs/hero.png", "docs/74hc00d-datasheet.pdf", "viewers/symbol.html",- "viewers/footprint.html"+ "viewers/footprint.html",+ "pads.json" ] }
pads.jsonadded+445@@ -0,0 +1,445 @@+{+ "schema": "adom.pads/1",+ "slug": "74hc00d",+ "footprint": "SOIC-14_3.9x8.7mm_P1.27mm",+ "generated_from": {+ "footprint": "SOIC-14_3.9x8.7mm_P1.27mm@sha256:a885b619b22880c9",+ "pins": "page.json:component.pins",+ "overrides": null+ },+ "pin1": {+ "pad": "1",+ "at": [+ -2.475,+ -3.81+ ],+ "corner": "top-left",+ "source": "silk-marker",+ "derived_from": "SOIC-14_3.9x8.7mm_P1.27mm@sha256:a885b619b22880c9"+ },+ "pad_count": 14,+ "paste_apertures": 0,+ "issues": [],+ "pads": [+ {+ "pad": "1",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ -3.81+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "1",+ "name": "1A",+ "type": "input",+ "description": "Gate 1 data input A. CMOS-level input (74HC00); high-impedance input with internal clamp diodes to VCC and GND. Combined with 1B in a 2-input NAND to produce 1Y.",+ "is_pin1": true,+ "source": {+ "geometry": "SOIC-14_3.9x8.7mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "2",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ -2.54+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "2",+ "name": "1B",+ "type": "input",+ "description": "Gate 1 data input B. CMOS-level input (74HC00); high-impedance input with internal clamp diodes to VCC and GND. Combined with 1A in a 2-input NAND to produce 1Y.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-14_3.9x8.7mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "3",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ -1.27+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "3",+ "name": "1Y",+ "type": "output",+ "description": "Gate 1 data output. Push-pull CMOS output: 1Y = NAND(1A, 1B). Drives up to ±5.2 mA at VCC = 6.0 V.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-14_3.9x8.7mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "4",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ 0.0+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "4",+ "name": "2A",+ "type": "input",+ "description": "Gate 2 data input A. CMOS-level input (74HC00); high-impedance input with internal clamp diodes to VCC and GND. Combined with 2B in a 2-input NAND to produce 2Y.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-14_3.9x8.7mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "5",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ 1.27+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "5",+ "name": "2B",+ "type": "input",+ "description": "Gate 2 data input B. CMOS-level input (74HC00); high-impedance input with internal clamp diodes to VCC and GND. Combined with 2A in a 2-input NAND to produce 2Y.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-14_3.9x8.7mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "6",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ 2.54+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "6",+ "name": "2Y",+ "type": "output",+ "description": "Gate 2 data output. Push-pull CMOS output: 2Y = NAND(2A, 2B). Drives up to ±5.2 mA at VCC = 6.0 V.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-14_3.9x8.7mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "7",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ 3.81+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "7",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference (0 V). All voltages in the datasheet are referenced to this pin.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-14_3.9x8.7mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "8",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ 3.81+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "8",+ "name": "3Y",+ "type": "output",+ "description": "Gate 3 data output. Push-pull CMOS output: 3Y = NAND(3A, 3B). Drives up to ±5.2 mA at VCC = 6.0 V.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-14_3.9x8.7mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "9",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ 2.54+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "9",+ "name": "3A",+ "type": "input",+ "description": "Gate 3 data input A. CMOS-level input (74HC00); high-impedance input with internal clamp diodes to VCC and GND. Combined with 3B in a 2-input NAND to produce 3Y.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-14_3.9x8.7mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "10",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ 1.27+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "10",+ "name": "3B",+ "type": "input",+ "description": "Gate 3 data input B. CMOS-level input (74HC00); high-impedance input with internal clamp diodes to VCC and GND. Combined with 3A in a 2-input NAND to produce 3Y.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-14_3.9x8.7mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "11",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ 0.0+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "11",+ "name": "4Y",+ "type": "output",+ "description": "Gate 4 data output. Push-pull CMOS output: 4Y = NAND(4A, 4B). Drives up to ±5.2 mA at VCC = 6.0 V.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-14_3.9x8.7mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "12",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ -1.27+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "12",+ "name": "4A",+ "type": "input",+ "description": "Gate 4 data input A. CMOS-level input (74HC00); high-impedance input with internal clamp diodes to VCC and GND. Combined with 4B in a 2-input NAND to produce 4Y.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-14_3.9x8.7mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "13",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ -2.54+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "13",+ "name": "4B",+ "type": "input",+ "description": "Gate 4 data input B. CMOS-level input (74HC00); high-impedance input with internal clamp diodes to VCC and GND. Combined with 4A in a 2-input NAND to produce 4Y.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-14_3.9x8.7mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "14",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ -3.81+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "14",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage. Operating range 2.0 V to 6.0 V for 74HC00 (4.5 V to 5.5 V for 74HCT00). Decouple to GND with a 100 nF ceramic capacitor placed close to the pin.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-14_3.9x8.7mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ }+ ]+}