# 74FCT3807ASOG

**RENESAS** · Clock Buffers, Drivers · SOIC-20-300mil

74FCT3807ASOG from RENESAS, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | input | Clock input with hysteresis, TTL compatible and can be driven from 3.3V or 5V components (VIH max 5.5V). |
| 2 | GND | power_in | Ground pin; multiple grounds reduce noise. |
| 3 | O1 | output | Clock output 1 of the 1:10 fanout. |
| 4 | VCC | power_in | 3.3V ± 0.3V supply pin; multiple supply pins reduce noise. |
| 5 | O2 | output | Clock output 2 of the 1:10 fanout. |
| 6 | GND | power_in | Ground pin; multiple grounds reduce noise. |
| 7 | O3 | output | Clock output 3 of the 1:10 fanout. |
| 8 | VCC | power_in | 3.3V ± 0.3V supply pin; multiple supply pins reduce noise. |
| 9 | O4 | output | Clock output 4 of the 1:10 fanout. |
| 10 | GND | power_in | Ground pin; multiple grounds reduce noise. |
| 11 | O5 | output | Clock output 5 of the 1:10 fanout. |
| 12 | O6 | output | Clock output 6 of the 1:10 fanout. |
| 13 | GND | power_in | Ground pin; multiple grounds reduce noise. |
| 14 | O7 | output | Clock output 7 of the 1:10 fanout. |
| 15 | VCC | power_in | 3.3V ± 0.3V supply pin; multiple supply pins reduce noise. |
| 16 | O8 | output | Clock output 8 of the 1:10 fanout. |
| 17 | GND | power_in | Ground pin; multiple grounds reduce noise. |
| 18 | O9 | output | Clock output 9 of the 1:10 fanout. |
| 19 | O10 | output | Clock output 10 of the 1:10 fanout. |
| 20 | VCC | power_in | 3.3V ± 0.3V supply pin; multiple supply pins reduce noise. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | SOIC-20-300mil |
| Category | Clock and Timing |
| Pins | 20 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input HIGH Level (input pins) | VIH | 2 |  | 5.5 | V | Guaranteed Logic HIGH Level | 3 |
| Input LOW Level (input and I/O pins) | VIL | -0.5 |  | 0.8 | V | Guaranteed Logic LOW Level | 3 |
| Input HIGH Level (I/O pins) | VIH | 2 |  |  | V |  | 3 |
| Input HIGH Current (input pins) | IIH | -1 |  | 1 | μA | VCC = Max., VI = 5.5V | 3 |
| Input HIGH Current (I/O pins) | IIH | -1 |  | 1 | μA | VI = VCC | 3 |
| Input LOW Current (input pins) | IIL | -1 |  | 1 | μA | VCC = Max., VI = GND | 3 |
| Input LOW Current (I/O pins) | IIL | -1 |  | 1 | μA | VI = GND | 3 |
| High Impedance Output Current (3-State Output Pins) | IOZH | -1 |  | 1 | μA | VCC = Max., VO = VCC | 3 |
| Input Power Off Leakage | IOFF | -1 |  | 1 | μA | VCC = 0V, VIN = 4.5V | 3 |
| Clamp Diode Voltage | VIK |  | -0.7 | -1.2 | V | VCC = Min., IIN = -18mA | 3 |
| Output HIGH Current | IODH | -36 | -60 | -110 | mA | VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V | 3 |
| Output LOW Current | IODL | 50 | 90 | 200 | mA | VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V | 3 |
| Output HIGH Voltage (IOH = -8mA) | VOH | 2.4 | 3 |  | V | VCC = Min., VIN = VIH or VIL, IOH = -8mA | 3 |
| Output LOW Voltage (IOL = 0.1mA) | VOL |  |  | 0.2 | V | VCC = Min., VIN = VIH or VIL, IOL = 0.1mA | 3 |
| Output LOW Voltage (IOL = 16mA) | VOL |  | 0.2 | 0.4 | V | VCC = Min., VIN = VIH or VIL, IOL = 16mA | 3 |
| Output LOW Voltage (IOL = 24mA) | VOL |  | 0.3 | 0.5 | V | VCC = Min., VIN = VIH or VIL, IOL = 24mA | 3 |
| Short Circuit Current | IOS | -60 | -135 | -240 | mA | VCC = Max., VO = GND | 3 |
| Quiescent Power Supply Current (ICCL, ICCH, ICCZ) | ICCL |  | 0.1 | 10 | μA | VCC = Max., VIN = GND or VCC | 3 |
| Quiescent Power Supply Current, TTL Inputs HIGH | ΔICC |  | 10 | 30 | μA | VCC = Max., VIN = VCC -0.6V | 2 |
| Dynamic Power Supply Current | ICCD |  | 0.31 | 0.45 | mA/MHz | VCC = Max., VIN = VCC / VIN = GND, input toggling, 50% duty cycle, outputs open | 2 |
| Total Power Supply Current | IC |  | 15.5 | 22.8 | mA | VCC = Max., VIN = VCC, input toggling VIN = GND, 50% duty cycle, outputs open, fi = 50MHz | 2 |
| Input Capacitance | CIN |  | 4.5 | 6 | pF | TA = +25°C, f = 1.0MHz, VIN = 0V | 2 |
| Output Capacitance | COUT |  | 5.5 | 8 | pF | TA = +25°C, f = 1.0MHz, VOUT = 0V | 2 |
| Propagation Delay tPLH, tPHL (commercial, CL = 30pF) | tPLH, tPHL | 1.5 |  | 4 | ns | CL = 30pF, f ≤ 67MHz | 4 |
| Output Rise Time (commercial, CL = 30pF table) | tR |  |  | 1.5 | ns | 0.8 to 2V (see figure 3) | 4 |
| Output Fall Time (commercial, CL = 30pF table) | tF |  |  | 1.5 | ns | 0.8 to 2V | 4 |
| Output skew (commercial, CL = 30pF table) | tSK(O) |  |  | 0.35 | ns |  | 4 |
| Pulse skew (commercial, CL = 30pF table) | tSK(P) |  |  | 0.35 | ns |  | 4 |
| Package skew (commercial, CL = 30pF table) | tSK(T) |  |  | 0.75 | ns |  | 4 |
| Propagation Delay tPLH, tPHL (commercial, CL = 50pF) | tPLH, tPHL | 1.5 |  | 4.3 | ns | CL = 50pF, f ≤ 40MHz | 4 |
| Output Rise Time (commercial, CL = 50pF table) | tR |  |  | 1.5 | ns | 0.8 to 2V (see figure 4) | 4 |
| Output Fall Time (commercial, CL = 50pF table) | tF |  |  | 1.5 | ns | 0.8 to 2V | 4 |
| Output skew (commercial, CL = 50pF table) | tSK(O) |  |  | 0.35 | ns |  | 4 |
| Pulse skew (commercial, CL = 50pF table) | tSK(P) |  |  | 0.35 | ns |  | 4 |
| Package skew (commercial, CL = 50pF table) | tSK(T) |  |  | 0.75 | ns |  | 4 |
| Propagation Delay tPLH, tPHL (commercial, 50Ω to VCC/2) | tPLH, tPHL | 1.5 |  | 3 | ns | 50Ω to VCC/2, CL = 10pF | 4 |
| Output Rise Time (commercial, 50Ω table) | tR |  |  | 1.5 | ns | 0.8 to 2V (see figure 1) | 4 |
| Output Fall Time (commercial, 50Ω table) | tF |  |  | 1.5 | ns | 0.8 to 2V, or 10Ω AC termination | 4 |
| Output skew (commercial, 50Ω table) | tSK(O) |  |  | 0.35 | ns | CL = 50pF | 4 |
| Pulse skew (commercial, 50Ω table) | tSK(P) |  |  | 0.35 | ns | see figure 2, f ≤ 100MHz | 4 |
| Package skew (commercial, 50Ω table) | tSK(T) |  |  | 0.65 | ns | outputs connected in groups of two | 4 |
| Terminal Voltage with Respect to GND (VCC terminals) | VTERM | -0.5 |  | 4.6 | V | VCC terminals (note 2) | 2 |
| Terminal Voltage with Respect to GND (input terminals) | VTERM | -0.5 |  | 7 | V | Input terminals (note 3) | 2 |
| Terminal Voltage with Respect to GND (outputs and I/O terminals) | VTERM | -0.5 |  |  | V | Outputs and I/O terminals (note 4); printed max is VCC+0.5 | 2 |
| Storage Temperature | TSTG | -65 |  | 150 | °C |  | 2 |
| DC Output Current | IOUT | -60 |  | 60 | mA |  | 2 |
| Supply voltage VCC (nominal 3.3 V, printed ± 0.3 V) | VCC | -0.3 | 3.3 | 0.3 | V | VCC = 3.3V ± 0.3V (DC electrical characteristics operating range) | 3 |
| Ambient operating temperature (commercial) | TA | 0 |  | 70 | °C | Commercial: TA = 0°C to +70°C (SOG, no I suffix) | 3 |
| Input Hysteresis | VH |  | 150 |  | mV |  | 3 |

## CAD (KiCad official)

- Symbol: `74FCT3807ASOG`
- Footprint: `Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm`
- 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files: `74fct3807asog-etched.step` / `74fct3807asog-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74fct3807asog.step` / `74fct3807asog.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [RENESAS datasheet](docs/74fct3807asog-datasheet.pdf) (9 pp, sha256 `bf19ac9fff114bff`, retrieved 2026-10-30, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/74fct3807asog-datasheet.pdf)