component
74CBTLV3253PGG
Public Made by Adomby adom
RENESAS Signal Switches, Multiplexers, Decoders, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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74CBTLV3253PGG
RENESAS · Signal Switches, Multiplexers, Decoders · TSSOP-16
74CBTLV3253PGG from RENESAS, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OE | input | Bank 1 output-enable input; a high level disconnects all 1A/1B switches, and it should be tied to VCC through a pullup resistor so the device is high-impedance during power up or down. |
| 2 | S1 | input | Select input S1 that, together with S0, chooses which B port is connected to the A port; VIH is 2V minimum at VCC 2.7V to 3.6V and VIL is 0.8V maximum. |
| 3 | 1B4 | bidirectional | Bank 1 switch port B4, a bidirectional channel with about 5Ω on-state resistance between it and port 1A when selected. |
| 4 | 1B3 | bidirectional | Bank 1 switch port B3, a bidirectional channel with about 5Ω on-state resistance between it and port 1A when selected. |
| 5 | 1B2 | bidirectional | Bank 1 switch port B2, a bidirectional channel with about 5Ω on-state resistance between it and port 1A when selected. |
| 6 | 1B1 | bidirectional | Bank 1 switch port B1, a bidirectional channel with about 5Ω on-state resistance between it and port 1A when selected. |
| 7 | 1A | bidirectional | Bank 1 common switch port A, which connects to one of 1B1 to 1B4 as set by S0, S1 and 1OE. |
| 8 | GND | power_in | Ground reference for the device. |
| 9 | 2A | bidirectional | Bank 2 common switch port A, which connects to one of 2B1 to 2B4 as set by S0, S1 and 2OE. |
| 10 | 2B1 | bidirectional | Bank 2 switch port B1, a bidirectional channel with about 5Ω on-state resistance between it and port 2A when selected. |
| 11 | 2B2 | bidirectional | Bank 2 switch port B2, a bidirectional channel with about 5Ω on-state resistance between it and port 2A when selected. |
| 12 | 2B3 | bidirectional | Bank 2 switch port B3, a bidirectional channel with about 5Ω on-state resistance between it and port 2A when selected. |
| 13 | 2B4 | bidirectional | Bank 2 switch port B4, a bidirectional channel with about 5Ω on-state resistance between it and port 2A when selected. |
| 14 | S0 | input | Select input S0 that, together with S1, chooses which B port is connected to the A port; VIH is 2V minimum at VCC 2.7V to 3.6V and VIL is 0.8V maximum. |
| 15 | 2OE | input | Bank 2 output-enable input; a high level disconnects all 2A/2B switches, and it should be tied to VCC through a pullup resistor. |
| 16 | VCC | power_in | Supply voltage, specified from 2.3V to 3.6V in normal range. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC | 2.3 | 3.6 | V | 2 | ||
| High-Level Control Input Voltage | VIH | 1.7 | V | VCC = 2.3V to 2.7V | 2 | ||
| High-Level Control Input Voltage | VIH | 2 | V | VCC = 2.7V to 3.6V | 2 | ||
| Low-Level Control Input Voltage | VIL | 0.7 | V | VCC = 2.3V to 2.7V | 2 | ||
| Low-Level Control Input Voltage | VIL | 0.8 | V | VCC = 2.7V to 3.6V | 2 | ||
| Operating Free-Air Temperature | TA | -40 | 85 | °C | 2 | ||
| Supply Voltage Range | VCC | -0.5 | 4.6 | V | 2 | ||
| Input Voltage Range | VI | -0.5 | 4.6 | V | 2 | ||
| Continuous Channel Current | 128 | mA | 2 | ||||
| Input Clamp Current | IIK | -50 | mA | VI/O < 0 | 2 | ||
| Storage Temperature | TSTG | -65 | 150 | °C | 2 | ||
| Input Clamp Voltage | VIK | -1.2 | V | Control Inputs, Data Inputs VCC = 3V, II = -18mA | 3 | ||
| Control Input Leakage Current | II | -1 | 1 | µA | Control Inputs VCC = 3.6V, VI = VCC or GND | 3 | |
| Data I/O Off-State Leakage Current | IOZ | 5 | µA | Data I/O VCC = 3.6V, VO = 0 or 3.6V, switch disabled | 3 | ||
| Power-Off Leakage Current | IOFF | 50 | µA | VCC = 0, VI or VO = 0 to 3.6V | 3 | ||
| Quiescent Supply Current | ICC | 10 | µA | VCC = 3.6V, IO = 0, VI = VCC or GND | 3 | ||
| Increase in Supply Current per Control Input | ΔICC | 300 | µA | Control Inputs VCC = 3.6V, one input at 3V, other inputs at VCC or GND | 3 | ||
| On-State Resistance | RON | 5 | 8 | Ω | VCC = 2.3V VI = 0 IO = 64mA | 3 | |
| On-State Resistance | RON | 27 | 40 | Ω | VI = 1.7V IO = 15mA | 3 | |
| On-State Resistance | RON | 5 | 7 | Ω | VI = 0 IO = 64mA | 3 | |
| On-State Resistance | RON | 10 | 15 | Ω | VI = 2.4V IO = 15mA | 3 | |
| Propagation Delay | tPD | 0.15 | ns | VCC = 2.5V ± 0.2V; A to B or B to A | 3 | ||
| Propagation Delay | tPD | 0.25 | ns | VCC = 3.3V ± 0.3V; A to B or B to A | 3 | ||
| Select Time | tSEL | 1 | 4.8 | ns | VCC = 2.5V ± 0.2V; S to A or B | 3 | |
| Select Time | tSEL | 1 | 4.5 | ns | VCC = 3.3V ± 0.3V; S to A or B | 3 | |
| Enable Time | tEN | 1 | 4.8 | ns | VCC = 2.5V ± 0.2V; S to B | 3 | |
| Enable Time | tEN | 1 | 4.5 | ns | VCC = 3.3V ± 0.3V; S to B | 3 | |
| Disable Time | tDIS | 1 | 5.1 | ns | VCC = 2.5V ± 0.2V; S to B | 3 | |
| Disable Time | tDIS | 1 | 5.3 | ns | VCC = 3.3V ± 0.3V; S to B | 3 | |
| Output Enable Time | tEN | 1 | 5 | ns | VCC = 2.5V ± 0.2V; OE to A or B | 3 | |
| Output Enable Time | tEN | 1 | 4.8 | ns | VCC = 3.3V ± 0.3V; OE to A or B | 3 | |
| Output Disable Time | tDIS | 1 | 5.5 | ns | VCC = 2.5V ± 0.2V; OE to A or B | 3 | |
| Output Disable Time | tDIS | 1 | 5.4 | ns | VCC = 3.3V ± 0.3V; OE to A or B | 3 |
CAD (KiCad official)
- Symbol:
74CBTLV3253PGG - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
74cbtlv3253pgg-etched.step/74cbtlv3253pgg-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74cbtlv3253pgg.step/74cbtlv3253pgg.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: RENESAS datasheet (6 pp, sha256
084de7dd29d54321, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).