# 74CBTLV3244PGG

**RENESAS** · Signal Switches, Multiplexers, Decoders · TSSOP-20

74CBTLV3244PGG from RENESAS, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OE | input | Output Enable for switches 1A/1B, active LOW; when HIGH the four switches are off and a high-impedance state exists between A and B. |
| 2 | 1A1 | bidirectional | Port A bit 1 of the first switch group, connected to 1B1 when 1OE is LOW and high impedance when 1OE is HIGH. |
| 3 | 2B4 | bidirectional | Port B bit 4 of the second switch group, connected to 2A4 when 2OE is LOW and high impedance when 2OE is HIGH. |
| 4 | 1A2 | bidirectional | Port A bit 2 of the first switch group, connected to 1B2 when 1OE is LOW and high impedance when 1OE is HIGH. |
| 5 | 2B3 | bidirectional | Port B bit 3 of the second switch group, connected to 2A3 when 2OE is LOW and high impedance when 2OE is HIGH. |
| 6 | 1A3 | bidirectional | Port A bit 3 of the first switch group, connected to 1B3 when 1OE is LOW and high impedance when 1OE is HIGH. |
| 7 | 2B2 | bidirectional | Port B bit 2 of the second switch group, connected to 2A2 when 2OE is LOW and high impedance when 2OE is HIGH. |
| 8 | 1A4 | bidirectional | Port A bit 4 of the first switch group, connected to 1B4 when 1OE is LOW and high impedance when 1OE is HIGH. |
| 9 | 2B1 | bidirectional | Port B bit 1 of the second switch group, connected to 2A1 when 2OE is LOW and high impedance when 2OE is HIGH. |
| 10 | GND | power_in | Ground reference for the device. |
| 11 | 2A1 | bidirectional | Port A bit 1 of the second switch group, connected to 2B1 when 2OE is LOW and high impedance when 2OE is HIGH. |
| 12 | 1B4 | bidirectional | Port B bit 4 of the first switch group, connected to 1A4 when 1OE is LOW and high impedance when 1OE is HIGH. |
| 13 | 2A2 | bidirectional | Port A bit 2 of the second switch group, connected to 2B2 when 2OE is LOW and high impedance when 2OE is HIGH. |
| 14 | 1B3 | bidirectional | Port B bit 3 of the first switch group, connected to 1A3 when 1OE is LOW and high impedance when 1OE is HIGH. |
| 15 | 2A3 | bidirectional | Port A bit 3 of the second switch group, connected to 2B3 when 2OE is LOW and high impedance when 2OE is HIGH. |
| 16 | 1B2 | bidirectional | Port B bit 2 of the first switch group, connected to 1A2 when 1OE is LOW and high impedance when 1OE is HIGH. |
| 17 | 2A4 | bidirectional | Port A bit 4 of the second switch group, connected to 2B4 when 2OE is LOW and high impedance when 2OE is HIGH. |
| 18 | 1B1 | bidirectional | Port B bit 1 of the first switch group, connected to 1A1 when 1OE is LOW and high impedance when 1OE is HIGH. |
| 19 | 2OE | input | Output Enable for switches 2A/2B, active LOW; when HIGH the four switches are off and a high-impedance state exists between A and B. |
| 20 | VCC | power_in | Supply voltage, 2.3 V to 3.6 V; both OE pins should be tied to VCC through a pullup resistor to hold the high-impedance state during power up or down. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC | 2.3 |  | 3.6 | V |  | 2 |
| High-Level Control Input Voltage | VIH | 1.7 |  |  | V | VCC = 2.3V to 2.7V | 2 |
| High-Level Control Input Voltage | VIH | 2 |  |  | V | VCC = 2.7V to 3.6V | 2 |
| Low-Level Control Input Voltage | VIL |  |  | 0.7 | V | VCC = 2.3V to 2.7V | 2 |
| Low-Level Control Input Voltage | VIL |  |  | 0.8 | V | VCC = 2.7V to 3.6V | 2 |
| Operating Free-Air Temperature | TA | -40 |  | 85 | °C |  | 2 |
| Supply Voltage Range | VCC | -0.5 |  | 4.6 | V |  | 2 |
| Input Voltage Range | VI | -0.5 |  | 4.6 | V |  | 2 |
| Continuous Channel Current |  |  |  | 128 | mA |  | 2 |
| Input Clamp Current | IIK |  |  | -50 | mA | VI/O < 0 | 2 |
| Storage Temperature | TSTG | -65 |  | 150 | °C |  | 2 |
| Input Clamp Voltage | VIK |  |  | -1.2 | V | VCC = 3V, II = -18mA; Control Inputs, Data Inputs | 3 |
| Control Input Leakage Current | II | -1 |  | 1 | µA | VCC = 3.6V, VI = VCC or GND | 3 |
| Data I/O Off-State Leakage Current | IOZ |  |  | 5 | µA | VCC = 3.6V, VO = 0 or 3.6V, switch disabled | 3 |
| Power-Off Leakage Current | IOFF |  |  | 50 | µA | VCC = 0, VI or VO = 0 to 3.6V | 3 |
| Quiescent Supply Current | ICC |  |  | 10 | µA | VCC = 3.6V, IO = 0, VI = VCC or GND | 3 |
| Supply Current Increase per Control Input | ΔICC |  |  | 300 | µA | VCC = 3.6V, one input at 3V, other inputs at VCC or GND | 3 |
| Control Input Capacitance | CI |  | 4 |  | pF | VI = 3V or 0 | 3 |
| Input/Output Off Capacitance | CIO(OFF) |  | 6 |  | pF | VO = 3V or 0, OE = VCC | 3 |
| On-State Resistance | RON |  | 5 | 8 | Ω | VCC = 2.3V, VI = 0, IO = 64mA | 3 |
| On-State Resistance | RON |  | 27 | 40 | Ω | VI = 1.7V, IO = 15mA | 3 |
| On-State Resistance | RON |  | 5 | 7 | Ω | VI = 0, IO = 64mA | 3 |
| On-State Resistance | RON |  | 10 | 15 | Ω | VI = 2.4V, IO = 15mA | 3 |
| Propagation Delay A to B or B to A | tPD |  |  | 0.15 | ns | VCC = 2.5V ± 0.2V | 3 |
| Propagation Delay A to B or B to A | tPD |  |  | 0.25 | ns | VCC = 3.3V ± 0.3V | 3 |
| Output Enable Time OE to A or B | tEN | 1 |  | 4.5 | ns | VCC = 2.5V ± 0.2V | 3 |
| Output Enable Time OE to A or B | tEN | 1 |  | 4 | ns | VCC = 3.3V ± 0.3V | 3 |
| Output Disable Time OE to A or B | tDIS | 1 |  | 4.5 | ns | VCC = 2.5V ± 0.2V | 3 |
| Output Disable Time OE to A or B | tDIS | 1 |  | 5 | ns | VCC = 3.3V ± 0.3V | 3 |

## CAD (KiCad official)

- Symbol: `74CBTLV3244PGG`
- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`
- 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files: `74cbtlv3244pgg-etched.step` / `74cbtlv3244pgg-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74cbtlv3244pgg.step` / `74cbtlv3244pgg.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [RENESAS datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8555036821562114048) (6 pp, sha256 `eb99408b57c53aa2`, retrieved 2026-10-20, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/74cbtlv3244pgg-datasheet.pdf)