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74C923WN

Public Made by Adom

by adom

HGSEMI Signal Switches, Multiplexers, Decoders, DIP-20. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.

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74C923WN

HGSEMI · Signal Switches, Multiplexers, Decoders · DIP-20

74C923WN from HGSEMI, in a DIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ROW Y1 input Row 1 key matrix input with on-chip pull-up (Irp -2 to -5 µA min/max at VCC=5V), pulled low by a closed switch when its column is scanned.
2 ROW Y2 input Row 2 key matrix input with on-chip pull-up device.
3 ROW Y3 input Row 3 key matrix input with on-chip pull-up device.
4 ROW Y4 input Row 4 key matrix input with on-chip pull-up device.
5 ROW Y5 input Row 5 key matrix input with on-chip pull-up device (74C923 only).
6 OSCILLATOR input Schmitt trigger oscillator input setting the keyboard scan rate, driven by an external clock or an external capacitor.
7 KEYBOUNCE MASK input Key bounce mask input where a single external capacitor sets the debounce period; omitting the capacitor defeats debounce.
8 COLUMN X4 output Column 4 open-drain scan output, driven low sequentially, with Ron of 500 to 1400 ohms at VCC=5V.
9 COLUMN X3 output Column 3 open-drain scan output, driven low sequentially.
10 GND power_in Ground supply pin.
11 COLUMN X2 output Column 2 open-drain scan output, driven low sequentially.
12 COLUMN X1 output Column 1 open-drain scan output, driven low sequentially.
13 DATA AVAILABLE output Goes high when a valid keyboard entry has been made and returns low when the key is released.
14 OUTPUT ENABLE input Active-low output enable that enables the 3-STATE data outputs when taken low.
15 DATA OUT E tri_state 3-STATE data output E of the last-key register, LPTTL compatible (74C923 only).
16 DATA OUT D tri_state 3-STATE data output D of the last-key register, LPTTL compatible.
17 DATA OUT C tri_state 3-STATE data output C of the last-key register, LPTTL compatible.
18 DATA OUT B tri_state 3-STATE data output B of the last-key register, LPTTL compatible.
19 DATA OUT A tri_state 3-STATE data output A of the last-key register, LPTTL compatible.
20 VCC power_in Positive supply voltage, 3V to 15V operating range.

Key specifications

Parameter Value
Manufacturer HGSEMI
Package DIP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating free-air temperature TA -40 85 °C 4
Storage Temperature Range TSTG -65 150 °C 4
Power Dissipation, Dual-In-Line PD 700 mW Dual-In-Line package 4
Operating VCC Range VCC 3 15 V 4
Lead Temperature TL 260 °C Soldering, 10 seconds 4
Positive-Going Threshold Voltage at Osc and KBM Inputs VT 3 3.6 4.3 V VCC = 5V, IIN ≥ 0.7 mA 5
Positive-Going Threshold Voltage at Osc and KBM Inputs VT 6 6.8 8.6 V VCC = 10V, IIN ≥ 1.4 mA 5
Positive-Going Threshold Voltage at Osc and KBM Inputs VT 9 10 12.9 V VCC = 15V, IIN ≥ 2.1 mA 5
Negative-Going Threshold Voltage at Osc and KBM Inputs VT 0.7 1.4 2 V VCC = 5V, IIN ≥ 0.7 mA 5
Negative-Going Threshold Voltage at Osc and KBM Inputs VT 1.4 3.2 4 V VCC = 10V, IIN ≥ 1.4 mA 5
Negative-Going Threshold Voltage at Osc and KBM Inputs VT 2.1 5 6 V VCC = 15V, IIN ≥ 2.1 mA 5
Logical 1 Input Voltage, except Osc and KBM Inputs VIN(1) 3.5 4.5 V VCC = 5V 5
Logical 1 Input Voltage, except Osc and KBM Inputs VIN(1) 8 9 V VCC = 10V 5
Logical 1 Input Voltage, except Osc and KBM Inputs VIN(1) 12.5 13.5 V VCC = 15V 5
Logical 0 Input Voltage, except Osc and KBM Inputs VIN(0) 0.5 1.5 V VCC = 5V 5
Logical 0 Input Voltage, except Osc and KBM Inputs VIN(0) 1 2 V VCC = 10V 5
Logical 0 Input Voltage, except Osc and KBM Inputs VIN(0) 1.5 2.5 V VCC = 15V 5
Row Pull-Up Current at Y1, Y2, Y3, Y4 and Y5 Inputs Irp -2 -5 µA VCC = 5V, VIN = 0.1 VCC 5
Row Pull-Up Current at Y1, Y2, Y3, Y4 and Y5 Inputs Irp -10 -20 µA VCC = 10V 5
Row Pull-Up Current at Y1, Y2, Y3, Y4 and Y5 Inputs Irp -22 -45 µA VCC = 15V 5
Logical 1 Output Voltage VOUT(1) 4.5 V VCC = 5V, IO = -10µA 5
Logical 1 Output Voltage VOUT(1) 9 V VCC = 10V, IO = -10µA 5
Logical 1 Output Voltage VOUT(1) 13.5 V VCC = 15V, IO = -10µA 5
Logical 0 Output Voltage VOUT(0) 0.5 V VCC = 5V, IO = 10µA 5
Logical 0 Output Voltage VOUT(0) 1 V VCC = 10V, IO = 10µA 5
Logical 0 Output Voltage VOUT(0) 1.5 V VCC = 15V, IO = 10µA 5
Column ON Resistance at X1, X2, X3 and X4 Outputs Ron 500 1400 VCC = 5V, VO = 0.5V 5
Column ON Resistance at X1, X2, X3 and X4 Outputs Ron 300 700 VCC = 10V, VO = 1V 5
Column ON Resistance at X1, X2, X3 and X4 Outputs Ron 200 500 VCC = 15V, VO = 1.5V 5
Supply Current ICC 0.55 1.1 mA Osc at 0V (one Y low), VCC = 5V 5
Supply Current ICC 1.1 1.9 mA Osc at 0V (one Y low), VCC = 10V 5
Supply Current ICC 1.7 2.6 mA Osc at 0V (one Y low), VCC = 15V 5
Logical 1 Input Current at Output Enable IIN(1) 0.005 1 µA VCC = 15V, VIN = 15V 5
Logical 0 Input Current at Output Enable IIN(0) 0.005 1 µA VCC = 15V, VIN = 0V 5
Logical 0 Input Voltage, except Osc and KBM Inputs (CMOS/LPTTL interface) VIN(0) 0.8 V VCC = 4.75V 5
Logical 1 Output Voltage (CMOS/LPTTL interface) VOUT(1) 2.4 V IO = 360µA, VCC = 4.75V 5
Logical 0 Output Voltage (CMOS/LPTTL interface) VOUT(0) 0.4 V IO = 360 µA, VCC = 4.75V 5
Output Source Current (P-Channel) ISOURCE -1.75 -3.3 mA VCC = 5V, VOUT = 0V, TA = 25℃ 6
Output Source Current (P-Channel) ISOURCE -8 -15 mA VCC = 10V, VOUT = 0V, TA = 25℃ 6
Output Sink Current (N-Channel) ISINK 1.75 3.6 mA VCC = 5V, VOUT = VCC, TA = 25℃ 6
Output Sink Current (N-Channel) ISINK 8 16 mA VCC = 10V, VOUT = VCC, TA = 25℃ 6
Propagation Delay Time to Logical 0 or Logical 1 from D.A. tpd0, tpd1 60 150 ns VCC = 5V, CL = 50 pF (Figure 1) 6
Propagation Delay Time to Logical 0 or Logical 1 from D.A. tpd0, tpd1 35 80 ns VCC = 10V, CL = 50 pF (Figure 1) 6
Propagation Delay Time to Logical 0 or Logical 1 from D.A. tpd0, tpd1 25 60 ns VCC = 15V, CL = 50 pF (Figure 1) 6
Propagation Delay Time from Logical 0 or Logical 1 into High Impedance State t0H, t1H 80 200 ns VCC = 5V, RL = 10k (Figure 2) 6
Propagation Delay Time from Logical 0 or Logical 1 into High Impedance State t0H, t1H 50 110 ns VCC = 15V (Figure 2) 6
Propagation Delay Time from High Impedance State to Logical 0 or Logical 1 tH0, tH1 100 250 ns VCC = 5V, RL = 10k (Figure 2) 6
Propagation Delay Time from High Impedance State to Logical 0 or Logical 1 tH0, tH1 55 125 ns VCC = 10V, CL = 50 pF (Figure 2) 6
Propagation Delay Time from High Impedance State to Logical 0 or Logical 1 tH0, tH1 40 90 ns VCC = 15V (Figure 2) 6
Input Capacitance CIN 5 7.5 pF Any Input (Note 4) 6
3-STATE Output Capacitance COUT 10 pF Any Output (Note 4) 6

CAD (KiCad official)

  • Symbol: 74C923WN
  • Footprint: Package_DIP:DIP-20_W7.62mm
  • 3D model: DIP-20 (KiCad packages3D, STEP)
  • 3D model files: 74c923wn-etched.step / 74c923wn-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74c923wn.step / 74c923wn.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HGSEMI datasheet (15 pp, sha256 2f2ce833dc038823, retrieved 2026-10-21, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF