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74AVC4T774PW-Q100J
Public Made by Adomby adom
Nexperia Translators, Level Shifters, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74AVC4T774PW-Q100J
Nexperia · Translators, Level Shifters · TSSOP-16
74AVC4T774PW-Q100J from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DIR1 | input | Direction control input for bit 1, referenced to VCC(A): HIGH allows transmission from A1 to B1 and LOW allows transmission from B1 to A1. |
| 2 | DIR2 | input | Direction control input for bit 2, referenced to VCC(A): HIGH allows transmission from A2 to B2 and LOW allows transmission from B2 to A2. |
| 3 | A1 | bidirectional | Data input or output, referenced to VCC(A); recommended input voltage range is 0 V to 3.6 V. |
| 4 | A2 | bidirectional | Data input or output, referenced to VCC(A); recommended input voltage range is 0 V to 3.6 V. |
| 5 | A3 | bidirectional | Data input or output, referenced to VCC(A); recommended input voltage range is 0 V to 3.6 V. |
| 6 | A4 | bidirectional | Data input or output, referenced to VCC(A); recommended input voltage range is 0 V to 3.6 V. |
| 7 | DIR3 | input | Direction control input for bit 3, referenced to VCC(A): HIGH allows transmission from A3 to B3 and LOW allows transmission from B3 to A3. |
| 8 | DIR4 | input | Direction control input for bit 4, referenced to VCC(A): HIGH allows transmission from A4 to B4 and LOW allows transmission from B4 to A4. |
| 9 | OE | input | Active-LOW output enable input, referenced to VCC(A); a HIGH puts An and Bn into the high-impedance OFF-state so the buses are isolated. |
| 10 | GND | power_in | Ground (0 V); if at least one of VCC(A) or VCC(B) is at GND level the device enters suspend mode with An and Bn high-impedance. |
| 11 | B4 | bidirectional | Data input or output, referenced to VCC(B); recommended input voltage range is 0 V to 3.6 V. |
| 12 | B3 | bidirectional | Data input or output, referenced to VCC(B); recommended input voltage range is 0 V to 3.6 V. |
| 13 | B2 | bidirectional | Data input or output, referenced to VCC(B); recommended input voltage range is 0 V to 3.6 V. |
| 14 | B1 | bidirectional | Data input or output, referenced to VCC(B); recommended input voltage range is 0 V to 3.6 V. |
| 15 | VCC(B) | power_in | Supply voltage B, which the Bn pins are referenced to; recommended range is 0.8 V to 3.6 V. |
| 16 | VCC(A) | power_in | Supply voltage A, to which the An, OE and DIRn inputs are referenced; recommended range is 0.8 V to 3.6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| HIGH-level input voltage (data input) | VIH | 1.6 | V | VCCI = 2.3 V to 2.7 V | 6 | ||
| HIGH-level input voltage (data input) | VIH | 2 | V | VCCI = 3.0 V to 3.6 V | 6 | ||
| HIGH-level input voltage (DIRn, OE input) | VIH | 1.6 | V | VCC(A) = 2.3 V to 2.7 V | 6 | ||
| HIGH-level input voltage (DIRn, OE input) | VIH | 2 | V | VCC(A) = 3.0 V to 3.6 V | 6 | ||
| LOW-level input voltage (data input) | VIL | 0.7 | V | VCCI = 2.3 V to 2.7 V | 6 | ||
| LOW-level input voltage (data input) | VIL | 0.8 | V | VCCI = 3.0 V to 3.6 V | 6 | ||
| LOW-level input voltage (DIRn, OE input) | VIL | 0.7 | V | VCC(A) = 2.3 V to 2.7 V | 6 | ||
| LOW-level input voltage (DIRn, OE input) | VIL | 0.8 | V | VCC(A) = 3.0 V to 3.6 V | 6 | ||
| HIGH-level output voltage | VOH | 0.85 | V | IO = -3 mA; VCC(A) = VCC(B) = 1.1 V | 6 | ||
| HIGH-level output voltage | VOH | 1.05 | V | IO = -6 mA; VCC(A) = VCC(B) = 1.4 V | 6 | ||
| HIGH-level output voltage | VOH | 1.2 | V | IO = -8 mA; VCC(A) = VCC(B) = 1.65 V | 6 | ||
| HIGH-level output voltage | VOH | 1.75 | V | IO = -9 mA; VCC(A) = VCC(B) = 2.3 V | 6 | ||
| HIGH-level output voltage | VOH | 2.3 | V | IO = -12 mA; VCC(A) = VCC(B) = 3.0 V | 6 | ||
| LOW-level output voltage | VOL | 0.1 | V | IO = 100 μA; VCC(A) = VCC(B) = 0.8 V to 3.6 V | 7 | ||
| LOW-level output voltage | VOL | 0.25 | V | IO = 3 mA; VCC(A) = VCC(B) = 1.1 V | 7 | ||
| LOW-level output voltage | VOL | 0.35 | V | IO = 6 mA; VCC(A) = VCC(B) = 1.4 V | 7 | ||
| LOW-level output voltage | VOL | 0.45 | V | IO = 8 mA; VCC(A) = VCC(B) = 1.65 V | 7 | ||
| LOW-level output voltage | VOL | 0.55 | V | IO = 9 mA; VCC(A) = VCC(B) = 2.3 V | 7 | ||
| LOW-level output voltage | VOL | 0.7 | V | IO = 12 mA; VCC(A) = VCC(B) = 3.0 V | 7 | ||
| input leakage current (DIRn, OE) | II | -5 | 5 | μA | DIRn, OE input; VI = 0 V or 3.6 V; VCC(A) = VCC(B) = 0.8 V to 3.6 V (±5 μA, -40 °C to +125 °C column) | 7 | |
| input leakage current (A or B port) | II | -30 | 30 | μA | A or B port; VO = 0 V or VCCO; VCC(A) = VCC(B) = 3.6 V | 7 | |
| OFF-state output current (suspend, A port) | IOZ | -30 | 30 | μA | suspend mode A port; VO = 0 V or VCCO; VCC(A) = 3.6 V; VCC(B) = 0 V | 7 | |
| OFF-state output current (suspend, B port) | IOZ | -30 | 30 | μA | suspend mode B port; VO = 0 V or VCCO; VCC(A) = 0 V; VCC(B) = 3.6 V | 7 | |
| power-off leakage current (A port) | IOFF | -30 | 30 | μA | A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V | 7 | |
| power-off leakage current (B port) | IOFF | -30 | 30 | μA | B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V | 7 | |
| supply current (A port) | ICC | 55 | μA | A port; VI = 0 V or VCCI; IO = 0 A; VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V | 7 | ||
| supply current (A port) | ICC | 50 | μA | A port; VI = 0 V or VCCI; IO = 0 A; VCC(A) = 1.1 V to 3.6 V; VCC(B) = 1.1 V to 3.6 V | 7 | ||
| supply current (A port) | ICC | -12 | μA | A port; VI = 0 V or VCCI; IO = 0 A; VCC(A) = 0 V; VCC(B) = 3.6 V | 7 | ||
| supply current (B port) | ICC | 55 | μA | B port; VI = 0 V or VCCI; IO = 0 A; VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V | 7 | ||
| supply current (B port) | ICC | 50 | μA | B port; VI = 0 V or VCCI; IO = 0 A; VCC(A) = 1.1 V to 3.6 V; VCC(B) = 1.1 V to 3.6 V | 7 | ||
| supply current (B port) | ICC | -12 | μA | B port; VI = 0 V or VCCI; IO = 0 A; VCC(A) = 3.6 V; VCC(B) = 0 V | 7 | ||
| supply current (A plus B) | ICC | 70 | μA | A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = 0 V or VCCI; VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V | 7 | ||
| supply current (A plus B) | ICC | 65 | μA | A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = 0 V or VCCI; VCC(A) = 1.1 V to 3.6 V; VCC(B) = 1.1 V to 3.6 V | 7 | ||
| additional supply current | ΔICC | 650 | μA | VI = 3.0 V; VCC(A) = VCC(B) = 3.6 V | 8 | ||
| supply voltage A | VCC(A) | -0.5 | 4.6 | V | 4 | ||
| supply voltage B | VCC(B) | -0.5 | 4.6 | V | 4 | ||
| input clamping current | IIK | -50 | mA | VI < 0 V | 4 | ||
| input voltage | VI | -0.5 | 4.6 | V | Note [1] applies | 4 | |
| output clamping current | IOK | -50 | mA | VO < 0 V | 4 | ||
| output voltage (active mode) | VO | -0.5 | V | Active mode; printed maximum is VCCO + 0.5 V (not expressible as a number) | 4 | ||
| output voltage (suspend or 3-state mode) | VO | -0.5 | 4.6 | V | Suspend or 3-state mode | 4 | |
| output current | IO | -50 | 50 | mA | VO = 0 V to VCCO (printed ±50 mA) | 4 | |
| supply current | ICC | 100 | mA | ICC(A) or ICC(B) | 4 | ||
| ground current | IGND | -100 | mA | 4 | |||
| storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C; derates 8.5 mW/K above 91 °C (SOT403-1) | 4 | ||
| supply voltage A | VCC(A) | 0.8 | 3.6 | V | 5 | ||
| supply voltage B | VCC(B) | 0.8 | 3.6 | V | 5 | ||
| input voltage | VI | 0 | 3.6 | V | 5 | ||
| output voltage (active mode) | VO | 0 | V | Active mode; printed maximum is VCCO | 5 | ||
| output voltage (suspend or 3-state mode) | VO | 0 | 3.6 | V | Suspend or 3-state mode | 5 | |
| ambient temperature | Tamb | -40 | 125 | °C | 5 | ||
| input transition rise and fall rate | Δt/ΔV | 10 | ns/V | VCCI = 0.8 V to 3.6 V | 5 |
CAD (KiCad official)
- Symbol:
74AVC4T774PW-Q100J - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
74avc4t774pw-q100j-etched.step/74avc4t774pw-q100j-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74avc4t774pw-q100j.step/74avc4t774pw-q100j.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (21 pp, sha256
22bdd5be9cc909e7, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).