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74AUP1G32GF
Public Made by Adomby adom
Nexperia Logic Gates, XSON-6(1x1). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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74AUP1G32GF
Nexperia · Logic Gates · XSON-6(1x1)
74AUP1G32GF from Nexperia, in a XSON-6(1x1). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | B | input | Data input B of the 2-input OR gate; recommended input voltage range is 0 V to 3.6 V. |
| 2 | A | input | Data input A of the 2-input OR gate; recommended input voltage range is 0 V to 3.6 V. |
| 3 | GND | power_in | Ground (0 V) reference for all voltages in the datasheet. |
| 4 | Y | output | Data output Y (Y = A OR B); output voltage is limited to 0 V to VCC in active mode. |
| 5 | n.c. | unconnected | Not connected on the XSON6 package. |
| 6 | VCC | power_in | Supply voltage; recommended operating range is 0.8 V to 3.6 V, with an absolute maximum of 4.6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | XSON-6(1x1) |
| Category | Logic |
| Pins | 6 |
CAD (KiCad official)
- Symbol:
74AUP1G32GF - Footprint:
Package_TO_SOT_SMD:SOT-886 - 3D model: XSON-6(1x1) (KiCad packages3D, STEP)
- 3D model files:
74aup1g32gf-etched.step/74aup1g32gf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74aup1g32gf.step/74aup1g32gf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (19 pp, sha256
b2fb95241a7a091f, retrieved 2026-10-09, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 74AUP1G32GF
**Nexperia** · Logic Gates · XSON-6(1x1)
74AUP1G32GF from Nexperia, in a XSON-6(1x1). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | B | input | Data input B of the 2-input OR gate; recommended input voltage range is 0 V to 3.6 V. |
| 2 | A | input | Data input A of the 2-input OR gate; recommended input voltage range is 0 V to 3.6 V. |
| 3 | GND | power_in | Ground (0 V) reference for all voltages in the datasheet. |
| 4 | Y | output | Data output Y (Y = A OR B); output voltage is limited to 0 V to VCC in active mode. |
| 5 | n.c. | unconnected | Not connected on the XSON6 package. |
| 6 | VCC | power_in | Supply voltage; recommended operating range is 0.8 V to 3.6 V, with an absolute maximum of 4.6 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | XSON-6(1x1) |
| Category | Logic |
| Pins | 6 |
## CAD (KiCad official)
- Symbol: `74AUP1G32GF`
- Footprint: `Package_TO_SOT_SMD:SOT-886`
- 3D model: XSON-6(1x1) (KiCad packages3D, STEP)
- 3D model files: `74aup1g32gf-etched.step` / `74aup1g32gf-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74aup1g32gf.step` / `74aup1g32gf.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Nexperia datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588912992284495872) (19 pp, sha256 `b2fb95241a7a091f`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/74aup1g32gf-datasheet.pdf)