component

74ALVC541PW

Public Made by Adom

by adom

Nexperia Buffers, Drivers, Receivers, Transceivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic74alvc541pwfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 5d ago
viewers 74alvc541pw: viewers · Ray 5d ago
74alvc541pw-etched.glb Publish 0.1.0 · Ray 5d ago
74alvc541pw-etched.step 74alvc541pw: factory component page (tier=mfr) · Ray 5d ago
74alvc541pw-hero.glb 74alvc541pw: hero GLB from the etched model (keeps the MPN mark) · Ray 5d ago
74alvc541pw-hero.overlay.json Publish 0.1.0 · Ray 5d ago
74alvc541pw.glb Publish 0.1.0 · Ray 5d ago
74alvc541pw.kicad_mod Publish 0.1.0 · Ray 5d ago
74alvc541pw.kicad_sym Publish 0.1.0 · Ray 5d ago
74alvc541pw.lbr Publish 0.1.0 · Ray 5d ago
74alvc541pw.step Publish 0.1.0 · Ray 5d ago
package.json Publish 0.1.0 · Ray 5d ago
page.json Set visibility: public · Ray 5d ago
README.md Publish 0.1.0 · Ray 5d ago

74ALVC541PW

Nexperia · Buffers, Drivers, Receivers, Transceivers · TSSOP-20

74ALVC541PW from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE0 input Output enable input (active LOW); a HIGH level on OE0 forces all Y outputs to the high-impedance OFF-state, and the outputs are enabled only when OE0 and OE1 are both LOW.
2 A0 input Data input for buffer channel 0; Schmitt-trigger input tolerant of slow rise and fall times and overvoltage tolerant to 3.6 V.
3 A1 input Data input for buffer channel 1; Schmitt-trigger input tolerant of slow rise and fall times and overvoltage tolerant to 3.6 V.
4 A2 input Data input for buffer channel 2; Schmitt-trigger input tolerant of slow rise and fall times and overvoltage tolerant to 3.6 V.
5 A3 input Data input for buffer channel 3; Schmitt-trigger input tolerant of slow rise and fall times and overvoltage tolerant to 3.6 V.
6 A4 input Data input for buffer channel 4; Schmitt-trigger input tolerant of slow rise and fall times and overvoltage tolerant to 3.6 V.
7 A5 input Data input for buffer channel 5; Schmitt-trigger input tolerant of slow rise and fall times and overvoltage tolerant to 3.6 V.
8 A6 input Data input for buffer channel 6; Schmitt-trigger input tolerant of slow rise and fall times and overvoltage tolerant to 3.6 V.
9 A7 input Data input for buffer channel 7; Schmitt-trigger input tolerant of slow rise and fall times and overvoltage tolerant to 3.6 V.
10 GND power_in Ground (0 V) reference for all device voltages.
11 Y7 tri_state Buffer data output channel 7 with 3-state capability; goes high-impedance when OE0 or OE1 is HIGH, with output current limited to ±50 mA.
12 Y6 tri_state Buffer data output channel 6 with 3-state capability; goes high-impedance when OE0 or OE1 is HIGH, with output current limited to ±50 mA.
13 Y5 tri_state Buffer data output channel 5 with 3-state capability; goes high-impedance when OE0 or OE1 is HIGH, with output current limited to ±50 mA.
14 Y4 tri_state Buffer data output channel 4 with 3-state capability; goes high-impedance when OE0 or OE1 is HIGH, with output current limited to ±50 mA.
15 Y3 tri_state Buffer data output channel 3 with 3-state capability; goes high-impedance when OE0 or OE1 is HIGH, with output current limited to ±50 mA.
16 Y2 tri_state Buffer data output channel 2 with 3-state capability; goes high-impedance when OE0 or OE1 is HIGH, with output current limited to ±50 mA.
17 Y1 tri_state Buffer data output channel 1 with 3-state capability; goes high-impedance when OE0 or OE1 is HIGH, with output current limited to ±50 mA.
18 Y0 tri_state Buffer data output channel 0 with 3-state capability; goes high-impedance when OE0 or OE1 is HIGH, with output current limited to ±50 mA.
19 OE1 input Output enable input (active LOW); a HIGH level on OE1 forces all Y outputs to the high-impedance OFF-state, and the outputs are enabled only when OE0 and OE1 are both LOW.
20 VCC power_in Supply voltage; recommended operating range is 1.65 V to 3.6 V, with an absolute maximum rating of 4.6 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 4.6 V 4
Input voltage VI -0.5 4.6 V 4
Output voltage VO -0.5 V output HIGH or LOW state 4
Output voltage VO -0.5 4.6 V output 3-state 4
Input clamping current IIK -50 mA VI < 0 V 4
Output clamping current IOK -50 50 mA VO > VCC or VO < 0 V 4
Output current IO -50 50 mA VO = 0 V to VCC 4
Supply current ICC 100 mA 4
Ground current IGND -100 mA 4
Storage temperature Tstg -65 150 °C 4
Total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 4
Supply voltage VCC 1.65 3.6 V 4
Input voltage VI 0 3.6 V 4
Output voltage VO 0 V output HIGH or LOW state 4
Output voltage VO 0 3.6 V output 3-state 4
Ambient temperature Tamb -40 125 °C 4
Input transition rise and fall rate Δt/ΔV 20 ns/V VCC = 1.65 V to 2.7 V 4
Input transition rise and fall rate Δt/ΔV 10 ns/V VCC = 2.7 V to 3.6 V 4
HIGH-level input voltage VIH 1.7 V VCC = 2.3 V to 2.7 V 5
HIGH-level input voltage VIH 2 V VCC = 2.7 V to 3.6 V 5
LOW-level input voltage VIL 0.7 V VCC = 2.3 V to 2.7 V 5
LOW-level input voltage VIL 0.8 V VCC = 2.7 V to 3.6 V 5
HIGH-level output voltage VOH 1.25 1.51 V IO = -6 mA; VCC = 1.65 V 5
HIGH-level output voltage VOH 1.8 2.1 V IO = -12 mA; VCC = 2.3 V 5
HIGH-level output voltage VOH 1.7 2.01 V IO = -18 mA; VCC = 2.3 V 5
HIGH-level output voltage VOH 2.2 2.53 V IO = -12 mA; VCC = 2.7 V 5
HIGH-level output voltage VOH 2.4 2.76 V IO = -18 mA; VCC = 3.0 V 5
HIGH-level output voltage VOH 2.2 2.68 V IO = -24 mA; VCC = 3.0 V 5
LOW-level output voltage VOL 0.2 V VI = VIH or VIL; IO = 100 μA; VCC = 1.65 V to 3.6 V 5
LOW-level output voltage VOL 0.11 0.3 V IO = 6 mA; VCC = 1.65 V 5
LOW-level output voltage VOL 0.17 0.4 V IO = 12 mA; VCC = 2.3 V 5
LOW-level output voltage VOL 0.25 0.6 V IO = 18 mA; VCC = 2.3 V 5
LOW-level output voltage VOL 0.16 0.4 V IO = 12 mA; VCC = 2.7 V 5
LOW-level output voltage VOL 0.23 0.45 V IO = 18 mA; VCC = 3.0 V 5
LOW-level output voltage VOL 0.3 0.55 V IO = 24 mA; VCC = 3.0 V 5
Input leakage current II -20 0.1 20 μA VI = VCC or GND; VCC = 3.6 V 5
OFF-state output current IOZ -80 0.1 80 μA VI = VIH or VIL; VCC = 1.65 V to 3.6 V; VO = 3.6 V or GND 5
Power-off leakage current IOFF -80 0.1 80 μA VI or VO = 0 V to 3.6 V; VCC = 0 V 5
Supply current ICC 0.2 80 μA VI = VCC or GND; IO = 0 A; VCC = 3.6 V 5
Additional supply current ΔICC 5 750 μA per input pin; VCC = 3.0 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A 5
Propagation delay An to Yn tpd 1 3 5.3 ns see Fig. 3; VCC = 1.65 V to 1.95 V 6
Propagation delay An to Yn tpd 1 2.2 3.8 ns see Fig. 3; VCC = 2.3 V to 2.7 V 6
Propagation delay An to Yn tpd 1 2.5 3.8 ns see Fig. 3; VCC = 2.7 V 6
Propagation delay An to Yn tpd 1 2.3 3.5 ns see Fig. 3; VCC = 3.0 V to 3.6 V 6
Enable time OEn to Yn ten 1 4.2 8.6 ns see Fig. 4; VCC = 1.65 V to 1.95 V 6
Enable time OEn to Yn ten 1 3.3 6.2 ns see Fig. 4; VCC = 2.3 V to 2.7 V 6
Enable time OEn to Yn ten 1 3.7 6.7 ns see Fig. 4; VCC = 2.7 V 6
Enable time OEn to Yn ten 1 3.3 5.6 ns see Fig. 4; VCC = 3.0 V to 3.6 V 6
Disable time OEn to Yn tdis 1 4.8 8.6 ns see Fig. 4; VCC = 1.65 V to 1.95 V 6
Disable time OEn to Yn tdis 1 3.1 5.2 ns see Fig. 4; VCC = 2.3 V to 2.7 V 6
Disable time OEn to Yn tdis 1 3.1 5.5 ns see Fig. 4; VCC = 2.7 V 6
Disable time OEn to Yn tdis 1 2.9 5.3 ns see Fig. 4; VCC = 3.0 V to 3.6 V 6

CAD (KiCad official)

  • Symbol: 74ALVC541PW
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: 74alvc541pw-etched.step / 74alvc541pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74alvc541pw.step / 74alvc541pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (14 pp, sha256 c803e31b4c73639e, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF